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vsp 94x2a primus powerful scan-rate converter including multistandard color decoder version b13/b14 e d i t i o n aug. 16, 2004 6 2 5 1 -552-1ds d a t a s h e e t m i c r o n a s m i c r o n a s
vsp 94x2a data sheet 2 aug. 16, 2004; 6251-552-1ds micronas contents page section title 4 1. introduction 51.1.features 7 2. functional description 7 2.1. cvbs front-end 7 2.1.1. source select 7 2.1.2. signal levels and gain control 8 2.1.3. clamping 9 2.1.4. synchronization 9 2.1.5. chroma decoder 12 2.1.6. luminance processing 13 2.2. rgb front-end 14 2.2.1. source select 14 2.2.2. signal magnitudes and gain control 15 2.2.3. clamping 15 2.2.4. digital prefiltering 15 2.2.5. rgb
contents, continued page section title data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 3 34 3. i 2 c bus interface 34 3.1. i 2 c bus slave address 34 3.1.1. i 2 c bus format 40 3.1.2. i 2 c bus list in alphabetical order 46 3.1.3. i 2 c bus command table 52 3.1.4. i 2 c bus command description 105 4. specifications 105 4.1. outline dimensions 106 4.2. pin connections and short descriptions for vsp 9402 and vsp 9412 1) 109 4.3. differing pin connections an d short descriptions for vsp 9412 110 4.4. pin configurations 112 4.5. pin circuits 114 4.6. electrical characteristics 114 4.6.1. absolute maximum ratings 117 4.6.2. recommended operating conditions 119 4.6.3. characteristics 119 4.6.3.1. general characteristics 121 4.6.3.2. i 2 c bus characteristics 123 5. application circuit 125 5.1. application overview 126 6. data sheet history
vsp 94x2a data sheet 4 aug. 16, 2004; 6251-552-1ds micronas powerful scan-rate converter including multistandard color decoder release note: revision bars indicate significant changes to the previous edition. 1. introduction the vsp 94x2a (primus) is a new component of the micronas megavision ? ic set in a cmos embed- ded dram technology. the vsp 94x2a comprises all main functions of a digital featurebox in one monolithic ic. the number of features is limited in favor of a low- cost solution, but no trade-off has been made concern- ing picture quality. the family is ideally suited to work in conjunction with the deflection processors sda 9380 (9402/32) and ddp 3315c (9412/42). in comb ination with the ?digital tv decoder? mde 9500, double-scan idtv is possible. the package is upward pin-compatible to other medium-range and high-end devices of the vsp 94xy family. a 50/60 hz derivative is also available (9432, 9442). the device comprises a digital multistandard color decoder, an rgb interface with fast-blank capa- bility (scart), digital it u656 input, scaling units including panorama, embedded dram for upconver- sion, picture improvements, temporal noise reduction, as well as a/d and d/a converters. table 1?1: primus? versions version scan rate conversion digital input digital output analog output 9402a (b13) 100i/120i ( ? ? ? ?? table 1?2: hardware compatibility and suited backend ics hardware compatible 1) suited backend ic ddp 3315c sda 9380 vsp 94 02a , vsp 94 05b , vsp 94 35b vsp 94 07b, vsp 94 37b ? ? 12a, vsp 94 15b , vsp 94 45b vsp 94 17b , vsp 94 47b ? 25b, vsp 94 27b ??
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 5 1.1. features ? integrated video matrix switch up to seven cvbs inputs, up to two y/c inputs, three cvbs outputs (y/c inputs signals are com- bined to cvbs output format) 9 bit amplitude resolution for cvbs, y/c a/d con- verter agc (automatic gain control) ? multi-standard color decoder pal/ntsc/secam includ ing all substandards automatic recognition of chroma standard only one crystal necessary for all standards ? rgb-fbl or yuv-h-v input 8 bit amplitude resolution for rgb or yuv 8 bit amplitude resolution for fbl or h ? itu656 support (version dependent, refer to next chapter) itu656 input/output ds656 output (double-scan ?656-like? output) ? letterbox detection ? noise reduction temporal noise reduction field-based temporal noise reduction for lumi- nance and chrominance different motion detectors for luminance and chrominance or identical flexible programming of the temporal noise reduction parameters automatic measurement of the noise level ? horizontal scaling of the 1f h signal split-screen possible with additional pip or text processor ? flexible digital horizontal scaling of the 2f h signal scaling factors: 3, ..., 0.75 including 16:9 compat- ibility 5 zone panorama generator ? embedded memory on-chip memory controller embedded dram core for field memory sram for pal/secam delay line ? data format 4:2:2 ? flexible clock and synchronization concept horizontal line-locked or free-running mode vertical locked or free-running mode ? scan-rate-conversion simple interlaced modes (100/120 hz): aabb, aaaa, bbbb (9402a/9412a only) no scan-rate-conversion modes (50/60 hz): ab, aa, bb (9432a/9442a only) ? flexible output sync controller flexible positioning of the output signal flexible programming of the output sync raster ?blank signal? generation ? signal manipulations still field insertion of colored background windowing vertical chrominance shift for improved vcr pic- ture quality ? sharpness improvement digital color transition improvement (dcti) peaking (luminance) ? three d/a converters 9 bit amplitude resolution for y, -(r-y), -(b-y) out- put 72 mhz clock frequency two-fold oversampling for anti-imaging simplification of extern al analog postfiltering ? 1920 active pixel/per line in default configuration ?i 2 c-bus control (400 khz) selectable i 2 c address ?1.8v
vsp 94x2a data sheet 6 aug. 16, 2004; 6251-552-1ds micronas fig. 1?1: block diagram 13 6 i2c interface (56) 19 adr/tdi scl sda v dac (54) u dac (53) y dac (52) offset gain 76 2 79 gain offset offset gain adc1 (2) 52 63 62 61 53 54 58 55 56 57 39 40 41 48 37 46 47 gain adc2 (3) gain source select (1) source select (16) 38 adcr (12) gain adcg (13) gain adcb (14) gain adcf (15) gain notch deskew (4) sync (6) color decoder (5) delay control (pal/secam) (7) 1h delay 18 20 anti-alias, deskew (17) anti-alias, deskew (18) anti-alias, deskew (19) anti-alias, deskew (20) test- controller, memory bist (55) 71 7 tclk tms 69 70 xtal oscillator (9) xout xin divider 32 31 30 15 22 21 16 10 9 74 8 itu656 decoder (41) 656hin/ clkf20 656vin/ blank clkf20 rgb yuv or bypass (25) (27) y brightness contrast (26) u,v saturation offset, gain (29) (30) soft-mix channel mux (31) down sampling 2 4:4:4 4:2:2 (28) h- prescaler (34) noise measure ment (32) clamping correction (21) clamping correction (22) clamping correction (23) dcti (46) peaking (45) coarse delay 4:4:4 (49) itu656 encoder (51) 8 8:8:8 (50) fine delay y noise reduction (38) uv noise reduction (37) edram memory controller (39) 14 23 17 27 (44) h- postscaler (42) panorama generator (43) v h avout auout ayout hout vout clkout v50 h50 v cvbso3 cvbso2 cvbso1 cvbs1 cvbs2 cvbs3 cvbs4 cvbs5 cvbs6 cvbs7 rin1 gin1 bin1 rin2 gin2 bin2 fbl2 fbl1 656clk 656io0 656io1 656io2 656io3 656io4 656io5 656io6 656io7 clamp clamp clamping signals to adcs agc generator y delay (8) primus (b13/b14) vsp 94x2a clkb36 y u,v cvbs/y c ycsel y u,v y u v f main insert clkf2pad uv in y in data buffer data buffer 24 reset line-locked or freerunning divider line-locked clocks (36, 72 mhz) freerunning clocks (20.25, 40.5 mhz) clamped, filterd sync signal output data controller (55) read control h/v- acquisition (33) input sync output sync background generator (57) output sync controller (40) 648 mhz dto (10) ll-pll (11) 648 mhz clk 216 mhz clk line-locked blank blanen blank fb 940xa, only 80 78 79 77 75 76 i656iclk 1 2 3 i656i0 i656i1 i656i2 i656i3 i656i4 i656i5 i656i6 i656i7 to 656decoder 941xa, only letterbox detection (58) pixel mixer
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 7 2. functional description all i 2 c bus registers mentioned are printed in bold and italics (e.g. ycdel ). 2.1. cvbs front-end the cvbs front-end consists of the color decoding cir- cuit itself, a sync processing circuit for generation of h/ v signals out of the cvbs signal, and the luminance processing. the main task of the luminance process- ing is to remove the color carrier by means of a notch filter. for pal and secam operation a baseband delay line is used for u and v signals. this can be used as comb filter in ntsc operation (only for chrominance). the rgb input can either be used as an overlay for the cvbs channel (rgb+fbl) or as a full mast er channel (rgb+h/v). the overlay is done by means of a soft- mix and can be used e.g. for ?scart? connector. this block contains a matrix (for rgb signals) which is switched off for yuv (e.g. ypbpr) input signals. a cbs (contrast, brightness, saturation) control makes the input signal adjustable. 2.1.1. source select fig. 2?1 shows the analog front-end. the analog cvbs signal can be fed to the inputs cvbs1...7 of vsp 94x2a (amplitude 0.5...1.5 v pp ). one signal is selected via cvbsel1 and fed to the first adc. a sec- ond signal is selected via cvbsel2 and fed to the other adc. cvbs4&5 or cvbs6&7 are intended to be use as separate y/c inputs ( ycsel ). after clamping to the back porch both signals are ad-converted with an amplitude resolution of 9 bit. the ad conversion is done using a 20.25 mhz freerunning stable crystal clock. before the a to d conversion the signals are lowpass filtered to avoid an tialias effects. three inputs can be looped back to output cvbso1-3 ( cvbosel1 , cvbosel2 , cvbosel3 ). a signal addition is performed to output a cvbs signal even when separate y/c signals are used at input. inputs that are not used are roughly clamped to fit in the allowed voltage region. for stand-by operation (power- down mode), a/d and d/a converter are switched off by standby keeping the source-selector operational. 2.1.2. signal levels and gain control to adjust to different c vbs input voltages a digitally working automatic gain control is implemented. input voltages in the range between 0.6 to 1.8 v pp can be applied to the cvbs inputs. for best signal-to-noise ratio the maximum available cvbs amplitude is recommended. the agc behavior can be chosen from four possible modes ( agcmd ) (see table 2?1). fig. 2?1: input selection table 2?1: agc modes agcmd agc operation mode 00 agc uses the height of the sync pulse as a reference and additionally reduces amplification when adc overflows 01 agc uses the height of the sync pulse as a reference 10 agc uses only adc overflows 11 agc is disabled and the adc fits to the values given in agcadj1 cvbs 1 cvbs 2 cvbs 3 cvbs 4 / y1 cvbs 5 / c1 cvbs 6 / y2 cvbs 7 / c2 c c c c c c c 1 / 9 1 / 9 1 / 9 1 / 9 1 / 9 filter filter c buffer buffer buffer adc_cvbs1 adc_cvbs2 cvbso1 cvbso2 cvbso3 clamping pulse of adc_cvbs1 or adc_cvbs2. shifting of signal to required input voltage range for cvbso1..3
vsp 94x2a data sheet 8 aug. 16, 2004; 6251-552-1ds micronas fig. 2?2: cvbs, y and c amplitude characteristics. when using the sync height based agc mode, the a/d gain increases or decreases depending on the incom- ing signal. when using overflow detection only, the gain is set to maximum and is reduced whenever an ?overflow? occurs. the signal is low pass filtered so that chrominance and noise are not used for detection. the threshold can be adjusted by pwthd . a setting of ?11? equals 511 and means an overflow of the adc. other settings react for a lower level. the gain only becomes higher when a change of the channel is detected or is manually reset by agcres . agcfrze holds the current agc value. a manual setting of the adcs gain control is possible using the parameters agcadj1 and agcadj2 . the conversion range (cr) is bigger than the signal range (sry, src) leaving a headroom for overshoots (see fig. 2?2). . fig. 2?3: cvbs adc characteristic 2.1.3. clamping the timing of the clamping (pulse) control signals for the analog inputs are derived from its corresponding cvbs input signal. the clamping algorithm works with a split measurement pulse and a clamping pulse. the measurement pulse is used to detect the clamping error. the clamping pulse is used to enable current sources for reducing the detected clamping errors. the start and length of the measurement signals are inde- pendently adjustable for both channels ( clmpst1 , clmpd1 , clmpst2 , clmpd2 ). the same applies for the clamping signals ( clmpst1s , clmpd1s , clmpst2s , clmpd2s ). clamping and measurement signals for rgb channel are not separate. clamping for these adc are con- trolled by clmpst2s and clmpd2s only. clamping can be suppressed for some lines by clmplow and clmphigh to ignore copyprotection information. no external sync signals are required. fig. 2?4: clamping signals 511 442 144 16 0 white black sry(1v nom.) cr (1.2v nom.) 511 446 256 64 0 src(0.89 v nom.) 75% chroma 100% chroma burst burst upper headroom lower headroom upper headroom 0 8 16 24 32 40 48 56 64 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 gain control characteristic agcadj1, agcadj2 (i2c) conversion range [v] clmpd2 clmpd1s clmpst1s clmpd1 clmpst1 clamping adc1 clmpd2s clmpst1s clmpst2 measurement adc1 measurement and clamping rgbf clamping adc2 measurement adc2
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 9 2.1.4. synchronization after elimination of the high frequent components of the cvbs signal by a low pass filter, horizontal and vertical sync pulses are separated. horizontal sync pulses are generated by a digital phase locked loop. the time constant can be adjusted between fast and slow behavior in four steps ( plltc ) to accommodate different input sources (e.g. vcr). the time-constant can be changed during normal operation without visi- ble picture degradation. a fine tuning of the pll time constant can be done by nsred . additional weak input signals from a satellite dish (?fish?) become more stable when satnr is enabled. vertical sync pulses are separated by integration of equalizing pulses. a vertical flywheel mode improves vertical sync separation for weak signals ( vflywhl, vflywhlmd ). additionally, v-syncs may be gated by vthrl and vthrh to reject invalid v-syncs (independently adjust- able for 50 and 60 hz sources) if no input signal is con- nected the device switches to a freeruning mode. the device can be configured to switch-on background color when no or only a weak signal is applied ( nos- igb ). 50 hz or 60 hz operation for sync separation may be forced separately or selected to work automat- ically ( flnstrd ). 2.1.5. chroma decoder the digital multistandard chroma decoder is able to decode ntsc and pal signals with a subcarrier fre- quency of 3.58 mhz and 4.43 mhz (pal b * /n/ 60 ? ,ntsc m/4.4) as well as secam signals with auto- matic standard detection. alternatively a standard can be forced. the demodulation is done with a regener- ated color-carrier. to enable a factory adjustment of the crystal frequency, the frequency of the regenerated subcarrier can be adjusted via scadj . for this pur- pose the crystal deviation ( scdev ) can be read out via i 2 c after chroma pll locking (indicated by scouten ) and can be stored in scadj . for test purposes, cpllof allows the opening of the chroma pll loop. for adjustment to the specific operational area an automatic norm detection is selectable. available 50 hz color standards are pal b, pal n and secam. available 60 hz color standards are ntsc m, pal m, pal60 and ntsc44. for each line standard, one or more color standards can be enabled for automatic chroma standard detection. please refer to table 2? 3: and table 2?4: for allowed combinations. the standard detection process can be set to slow or fast behavior ( locksp ). in slow behavior, 25 fields are used to detect the standard, whereas 15 fields are used in fast behavior. if the detection was not success- ful during this time frame, the system will switch to the next enabled tv standard. table 2?2: clamping adjustment signal description clmpst1 measurement pulse start for adc1 clmpd1 measurement pulse duration for adc1 clmpst1s clamping pulse start for adc1 clmpd1s clamping pulse duration for adc1 clmpst2 (measurement pulse start for adc2) clmpd2 (measurement pulse duration for adc2) clmpst2s measure and clamp start for rgbf-adc (clamping start for adc2) clmpd2s measure and clamp duration for rgbf-adc (clamping duration for adc2 * pal b is representative for pal b/g/h/i/n ? pal60 and ntsc44 are nonstandard signals which are generated by some vcr or dvd player
vsp 94x2a data sheet 10 aug. 16, 2004; 6251-552-1ds micronas in addition, a standard can be forced as well. amstd50 selects whether pal b or secam is tried first in the automatic routine. amstd60 selects whether ntsc44/pal60 or ntsc m is tried first. both bits can also be set for automatic detection, then the last detected chroma standard will be used. for secam detection, a choice between different recogni- tion levels is possible ( scmidl, scmrel ) and the evaluated burst position is shiftable ( bgpos ). color standard ( stdet ), line standard ( lnstdrd ) and color killer status ( ckstat ) can be read out. an automatic chroma control (acc) produces a sta- ble output for input chroma variations from (approxi- mately) -30 db to +6 db compared to nominal burst value. the acc reference value is programmable for ntsc and pal independently ( ntscref , pa lr e f ) to ensure correct color saturation. with accfix , the acc is dis- abled and a constant value (dependent on ntscref and pa l r e f ) is used instead. accfrz holds the current acc value. the maximum amplification of the acc can be limited by acclim. this results a smooth attenu ation of color intensity for weak color carrier (see fig. 2?5). fig. 2?5: color killer adjustment table 2?3: allowed combinations for color-standard search (50 hz) standard cstand (50 hz) d2 d1 d0 none 0 00 pa l n 0 01 pa l b 0 10 secam 1 00 automatic pal bg / secam 1 10 table 2?4: allowed combinations for color-standard search (60 hz) standard cstand (60 hz) d6 d5 d4 d3 pal m 0010 ntsc m 0100 ntsc44 1000 automatic pal m / ntsc m 0110 automatic ntsc m / ntsc44/pal60 1100(!) acclim con ckill u,v attenuation of color-carrier +6db -4db +0db color off cons ckills u,v attenuation of color-carrier +6db -4db +0db color off pal, ntsc operation secam operation
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 11 if the chrominance signal is below an adjustable threshold ( ckill (pal; ntsc) or ckills (secam)) the color is switched off. to prevent on / off switching, a hysteresis is given by con or cons which is the value of switching on the color. colon switches on the color under any circumstance. the output of the color decoder can be set to uv or crcb data by crcb. for ntsc only, the color impres- sion (tint) can be adjusted by the hue control between -88 hue ). low chrominance values (+/- 1...3 lsb) may be deleted by uv-coring ( uvcor ). the chroma bandwidth can be adjusted by chrf . the setting value of chrf has no linear impact to the chroma bandwidth. the frequency response of the chroma bandfilter are shown in figure 2-7. also a filter with asymmetrical characteristic around the color carr ier is available ( ifcomp ) (figure 2?7). for secam mode, the de-emphasis filter can be adjusted by deempfir and deempiir . the bell filter can be adjusted by bellfir and belliir . the delay between y and c is well aligned and can also be adjusted in steps of 50 ns ( ycdel ). no picture shifting occurs when switching between different color standards (e.g. secam -> pal). a delay-line is imple- mented for pal and secam signals. it acts as a sim- ple chrominance comb-filter for ntsc and can be dis- abled by comb. this improves the vertical chroma resolution, but cross-color remains. fig. 2?6: chroma filter characteristics fig. 2?7: if prefilter 0 0.5 1 1.5 2 2.5 3 3.5 4 40 35 30 25 20 15 10 5 0 5 chroma filter frequency (mhz) damping (db) chrf=?001100? chrf=?001000? chrf=?001001? chrf=?111001? chrf=?001110? 4.433 3.58 0 1 2 3 4 5 6 30 25 20 15 10 5 0 5 10 if prefilter frequency (mhz) damping (db) ifcomp=?000? ifcomp=?011? ifcomp=?001? ifcomp=?010? ifcomp=?100?
vsp 94x2a data sheet 12 aug. 16, 2004; 6251-552-1ds micronas 2.1.6. luminance processing a luminance notch filter is implemented to separate the chroma information from the luminance. depend- ing on the color standard, one out of three different notch characteristics is chosen (?pal?, ?ntsc?, ?secam?) automatically. for pal and secam the respective notch filters have 5 different characteristics each. the luminance notch fil- ter for ntsc can be set to 4 different filter response curves. they can be selected by ntchsel . alterna- tively, no notch should be used for y/c input ( notchoff ). the filter characteristics can be found in figure 2?8 . in secam operation, the notch filter can be fixed to one frequency or toggle between 4.4 mhz and 4.25 mhz depending on the transmitted color (dr, db) ( secntch ). a simple lowpass-filter can be enabled by lppost to further reduce high-frequency noise component from the cvbs signal. fig. 2?8: filter characteristics for ntsc, pal m and pa l n fig. 2?9: filter characteristics for pal b/g, ntsc44, pa l 6 0 fig. 2?10: filter characteristics for secam ( secntch =?01?, 4.25 mhz) fig. 2?11: filter characteristics for y/c mode. the black level can be shifted by the parameter lmofst . this is required to compensate 7.5 ire off- sets in some input signals (e.g. ntsc) the positive or negative offset is added to the y signal before scaling. fig. 2?12: adjustment of ?black? to ?blankingvalue? at analog output. 3.58 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 30 25 20 15 10 5 0 5 characteristic for ntsc frequency [mhz] attenuation [db] ?x00? ntchsel= ?x01? ?x10? ?x11? 4.43 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 30 25 20 15 10 5 0 5 characteristic for pal frequency [mhz] attenuation [db] ntchsel= ?000? ?100? ?010? ?011? ?001? 4.25 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 30 25 20 15 10 5 0 5 characteristic for secam (4.25 mhz) frequency [mhz] attenuation [db] ntchsel= ?000? ?100? ?010? ?011? ?001? 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 30 25 20 15 10 5 0 5 characteristic for y/c frequency [mhz] attenuation [db] lppost=1 lppost=0 lmofst='01' lmofst='11' lmofst='00' lmofst='10' blanking black lmofst='01' lmofst='11' lmofst='00' lmofst='10' blanking black input signals without 7.5ire offset input signals with 7.5ire offset
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 13 2.2. rgb front-end an analog rgb input port for an external rgb or yuv source is available. the incoming signal is clamped to the back porch by a clamping pulse. as the memory is only able to store a 4:2:2 picture, the yuv input signal is downconverted to 4:2:2. there are two operation modes available. the first one uses this input as an overlay input (soft mix). the rgb or yuv signal must then be synchronized to t he main cvbs/yc signal. the second so called independent mode uses rgb / yuv including sync or h/v signals. this can be used, for example, for a dvd player or set-top-box. when using h sync from a non c vbs input (e.g. separate h- sync) this must be indicated by hinp . the usage of separate v sync must be set by vinp . the delay of luminance and fast-blank can be adjusted by yfdel , and chrominance can be delay adjusted by uvdel . if necessary, a fine adjustment of the fast blank can be set by the parameter fbldel . fig. 2?13: signal and clamping organization table 2?5: possible input signals for rgb front-end input signal fbl in v in sync separation remark hinp vinp rgb cvbs 1) sync on cvbs 1 0 yuv cvbs 1) sync on cvbs 1 0 rgb h 1) v sync on h e.g. set-top-box 1 1 yuv h 1) v sync on h e.g. set-top-box 1 1 rgb fbl synchron to cvbs/yc soft mix 0 0 yuv fbl synchron to cvbs/yc soft mix 0 0 rgb (incl. sync) sync on g (maybe on r/b) no external sync 1 0 yuv (incl. sync) sync on y no external sync e.g. dvd 1 0 1) instead of fbl input, cvbs i nput can be used when hinp=0 clampsignals 1 vinp adc2 adc1 adcr adcg adcb adcf from cvbs source select from cvbs source select from rgb source select from rgb source select from rgb source select from rgb source select data b data f datag data r data 2 sync processing adcsel hinp from vinp pin clampsignals2 dclmpf clmpvrb clmpvg clmpvrb agcadjf agcadjb agcadjg agcadjr agcadj2 agcadj1 clmpv1 256 agcmd r processing g processing b processing f processing to soft-mix to soft-mix to soft-mix to soft-mix rboffset goffset rboffset 0 1 01
vsp 94x2a data sheet 14 aug. 16, 2004; 6251-552-1ds micronas 2.2.1. source select two inputs are available. the choice between the first or second input is made by rgbsel . 2.2.2. signal magnitudes and gain control the gain adjustment of the four adcs can be done with the parameters agcadjr , agcadjg , agc- adjb , agcadjf fig. 2?14: y/rgbf amplitude characterist ics (with or without sync) fig. 2?15: uv amplitude characteristics fig. 2?16: rgb adc characteristic, fast-blank adc with clamping ( dclmpf =0) fig. 2?17: fast-blank adc char acteristic without clamping ( dclmpf =1) cry = 1.2 vpp 0 16 229 255 80 upper headroom lower headroom cry = 0.84 vpp 0 255 upper headroom 16 229 sry = 1 vpp sry = 0.7 vpp lower headroom cruv = 0.8 vpp sruv = 0.7 vpp 0 16 128 240 255 212 44 cruv = 0.8 vpp sruv = 0.7 vpp 0 16 128 240 255 212 44 lower headroom upper headroom upper headroom lower headroom 100% u 75% u 100% v 75% v 0 8 16 24 32 40 48 56 64 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 gain control characteristic agcadjr, agcadjg, agcadjb, agcadjf (i2c) conversion range [v] 0 8 16 24 32 40 48 56 64 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 dc gain control characteristic agcadjf (i2c) conversion range [v] adc output=255 adc output=0 conversion range
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 15 2.2.3. clamping when using the dynamic softmix-mode with fast-blank, clamping of fast-blank input must be disabled by dclmpf . the analog clamping value of red and blue input (v and u resp.) can be adjusted by clmpvrb . the analog clamping value of green input (y resp.) can be adjusted by clmpvg . depending on the input sig- nal format (yuv, rgb, sync signal or not) these bits must be set accordingly. on the digital side, a correc- tion of the analog clamping value must be performed to reconstruct the blacklev el. this is achieved by rbo- fst and gofst . (see table 2?6 on page 15) 2.2.4. digital prefiltering a digital prefiltering can be enabled. a band limitation is required, because the fo llowing deskewing filter per- forms best at frequencies of below 14 mhz. the filter- ing is performed in all four channels and can be dis- abled by aabyp . for signal conversion to 4:2:2, an additional chrominance lowpass can be enabled by chrsf . the deskewing filter can be disabled by skewsel . this is necessary when using the h50-pin in connection with a micronas picture-in-picture device (e.g. sda 938x, sda 948x, sda 958x). in this applica- tion, the rgb input (in1, in2, in3) of the pip can not be used for other rgb/yuv signals (e.g. ?scart? is not possible). as there is a pixel skew on h50, this pin is not suited to synchronize any ic, except for the above mentioned pip ics fig. 2?18: digital prefiltering of rgb input 2.2.5. rgb yuv matrix rgb or yuv signals are selected by yuvsel . the matrix coefficients are set according to itu recommen- dations. fig. 2?19: rgb to yuv matrix table 2?6: configurations of input signals mode clmpvg clmpvrb gofst rbofst dclmpf yuv, sync on y 80 128 64 128 don?t care yuv, sync on h,v 16 128 0 128 0 (clamping enabled) rgb, sync on g 80 16 64 0 don?t care rgb, sync on rgb 80 80 64 64 don?t care rgb, sync on h,v 16 16 0 0 0 (clamping enabled) rgb with fast-blank, synchron to cvbs 16 16 0 0 1 (clamping disabled) yuv with fast-blank, synchron to cvbs 16 128 0 128 1 (clamping disabled) 3 0 5 10 15 20 40 30 20 10 0 10 rgb-prefiltering frequency [mhz] attenuation [db] y u v r g b 0,299 0,587 0,114 0,147 ? 0,289 ? 0,436 0,615 0,515 ?0,100 ? ? =
vsp 94x2a data sheet 16 aug. 16, 2004; 6251-552-1ds micronas 2.2.6. contrast, brightness and saturation control of input signal the yuv signal can be manipulated in order to fit to the main channel. the contrast can be adjusted between 0 and 1.97 in 64 steps ( conadj ). the brightness is adjustable in 255 steps ( brtadj ). due to the independent chroma adjustment of u and v (64 steps each, usatadj , vsatadj ), uv as well as crcb input signals can both be displayed correctly. 2.2.7. soft mix the soft-mixer circuit consists of a fast blank (fb) processing block supplying a mixing factor k (0... 128) achieving the output function: k= ?0? means that only the main signal is fed through to the output. k= ?128? means that only the inserted signal becomes visible. the soft mixer supports four modes that are selected by mixop and smop. 2.2.8. static switch mode in its simplest and most common application the soft- mixer is used as a static switch between yuvmain and yuvinsert. this for instance the adequate way to han- dle a dvd component signal. by using mixop , k is internally set to 0 or 128 respectively. 2.2.9. static mixer mode the signal yuvmain and the component signal yuvin- sert may also be statically mixed. in this environment, k is manually controlled via fbloffset and mix- gain . all necessary limitation and rounding operations are built-in to fit the range: 0 mixgain =3, k is obtained by the mixing is only controlled by fbloffst . in the static mixer mode as well as in the previously mentioned static switch mode, the softmixer operates independently of the analog fast blank input. 2.2.10. dynamic mixer mode in the dynamic mixer mode, the mixer is controlled by the fast blank signal. the vspa provides a linear mix- ing coefficient the dynamic mode is used for mixing which is depen- dent on fb input. fb is the preprocessed digitized fast- blank input in the range from 0...127. fbl manipulation is done both for luminance and chrominance fbl sig- nal. fast blank is delay adjustable by fbldel in the range of -2...4 clock cycles. 2.2.11. fbl activity and overflow detection it is important to know whether the fbl input is used or not. therefore a detection circuit gives information via the i 2 c bus to the microcontroller. the circuit uses the fbl value as input. if it is greater than a threshold for one or five clock cycles ( fblconf ), the i 2 c regis- ter fblactive is set. this register is reset after a read access by the microcontroller. pfbl , pg , pr , pb indicate an overflow of the corresponding adc (upper limit: adc= 255) exceeding 5 clock cycles duration. table 2?7: rgb operation modes mixop smop soft mix mode 00 0 dynamic soft mix ( dectwo must be set to ?1?) 00 1 static soft mix ( dectwo must be set to ?1?) 01 x only rgb/yuv path visible 10 x only cvbs path visible 11 x (reserved) yuvmix yuv main 128 k ? () yuv inserted k ? + ? 128 -------------------------------------------------------------------------------------------- - = [ kmixgain 31 fbloffst ? () 32 + ? = k 158 3 fbloffst ? ? = k mixgain fb fbloffst 2 ? ? () 2 ----------------------------------------------------------------------------------- - 64 + =
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 17 2.3. input processing fig. 2?20: image format before memory 2.3.1. horizontal prescaler the main application of the horizontal prescaler is the conversion of the number of pixels coming form the 40.5/20.25 mhz pixel clock domain down to the num- ber of pixels stored in the memory (factor 2/3). gener- ally the number of incoming pixels can be decimated by a factor between 1 and 64 in a granularity of 2 out- put pixels. the horizontal scaler reduces the number of incoming pixels by subsampling. to prevent the intro- duction of alias distortion low pass filters are used for luminance and chrominance processing (fig. 2?22). in case of itu656 input, the lowpass filter must be dis- abled by haapresc . the horizontal prescaler consists of two main subsam- pling stages. the first stage is a scaler for rational dec- imation factors in a range of 1 to 2, controlled by hscpresc . the second stage decimates in integer steps (1,2,3,4...32), controlled by hdcpresc . fig. 2?21: y-decimation filter characteristics for standard operation (decimation=1.5) fig. 2?22: uv-decimation filter characteristic for standard operation (decimation=1.5) 2.3.2. noise reduction the fig. 2?23 shows a block diagram of the temporal noise reduction. the structure of the temporal motion adaptive noise reduction is the same for luminance as for chrominance signal. noise reduction is enabled by nron . the output of the motion detector is weighted using the parameters tnrclc and tnrcly . the look-up table input value range is separated into 8 segments. it is possible to freely program different behavior of the noise reduction by using predefined curve characteris- tic for each segment. the curve characteristics can be programmed by the parameters tnrsxy for lumi- nance and tnrsxc for chrominance. the curve-start is defined by tnrssy ( tnrssc ) at the end of the last segment (figure 2?24). the overall curve is now con- structed by connecting the end of segment 6 to the beginning of segment 7 and so on. negative values of ky (kc) are not possible and clipped to zero. for chrominance, the result of the luminance motion detector or a separate chorminance motion detector can be used ( tnrsel ). applip (active pixel per line input) hsync nalpfip (not active lines input) alpfip (active lines input) complete picture area napplip (not active pixel per line input) active picture vsync 0 1.25 2.5 3.75 5 6.25 7.5 8.75 10 40 35 30 25 20 15 10 5 0 5 y-decimation filter frequency [mhz] attenuation [db] 3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 40 35 30 25 20 15 10 5 0 5 uv decimation filter frequency (mhz) attenuation (db)
vsp 94x2a data sheet 18 aug. 16, 2004; 6251-552-1ds micronas fig. 2?23: temporal noise reduction fig. 2?24: segments of lut motion detection y lut y noise reduction y ky tnrcly tnrsxy y in y delay y in y delay y out motion detection c lut c noise reduction c kc tnrclc tnrsxc uv in uv delay uv in uv delay uv ou t tnrabs tnrsel nron kuv tnrsx=0000 tnrsx=0001 tnrsx=0010 tnrsx=0011 tnrsx=0100 tnrsx=0101 tnrsx=0110 tnrsx=0111 tnrsx=1000 tnrsx=1001 tnrsx=1010 tnrsx=1011 tnrsx=1100 tnrsx=1101 tnrsx=1110 tnrsx=1111
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 19 fig. 2?25: predefined curve characteristics for lut 2.3.3. noise measurement the noise measurement algorithm can be used to change the parameters of the temporal noise reduction processing depending on the actual noise level of the input signal. this is done by the tv- microcontroller which reads the noise level ( noiseme ), and sends different parameter sets to the temporal noise reduc- tion registers of the vsp 94x2a depending on this value (0 = no noise, 126 = strong noise). value 127 indicates an overflow status which means that the measurement failed. the value is determined by aver- aging over several fields. the line taken for noise mea- surement is selected by nmline . when noiseme contains updated data which were not read so far, nmstatus is set. nmstatus is reset when read. the measurement position can be adjusted ( nmpos ) as well as the sensitivity ( nmsense ). 2.3.4. letterbox detection a drawback of wide screen 16:9 tv sets are the black bars at the left and the right side on the screen, if dis- playing a 4:3 source on a 16:9 screen with correct aspect ratio. in case of letterbox source material also black bars at the top and bottom exist. with the help of an expansion algorithm it is possible to expand the let- terbox picture vertically and horizontally in such a way, that the lett erbox picture will fill the complete screen without loosing information. to do so, the information about the active part of the letterbox picture is neces- sary. active part means the information about the first active line and the last active line of the letterbox pic- ture. the figure below shows the principle of this idea. the wss (wide screen signal) signal contains some information about the picture format (4:3 or 14:9 or 16:9), but not all existing formats are covered and not all signals contain wss. therefore a separate algo- rithm is necessary which delivers the necessary infor- mation. the figure below shows the concept of the let- terbox detection algorithm. one part of the algorithm is dedicated hardware and located in the vsp 94x2a another part is software and located in the ram of the tv microcontroller. the pa rt located in vsp 94x2a is called measurement part. the measurement part delivers 5 signals to the controller part.based on the delivered information the controller part calculates an expansion and a vertical pan factor and sends these values back to the vsp 94x2 a for manipulation of the video signal. fig. 2?26: handling of letterbox pictures on 16:9 tubes ky/kc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 4 8 12 20 28 36 48 64 motion segment 0 segment 1 segment 2 segment 3 segment 4 segment 5 segment 6 segment 7 tnrssy, tnrssc 0000 0000 0100 0100 0100 1111 1111 0001 tnrsy , tnrsc 4:3 letterbox picture expanded letterbox picture
vsp 94x2a data sheet 20 aug. 16, 2004; 6251-552-1ds micronas fig. 2?27: hw/sw partitioning the letterbox detection block works only at a data rate of 13.5 mhz. due to the fact, that the input data rate at channel-mux output can be 13.5 mhz, 20.25 mhz or 40.5 mhz, the input signal has to be downsampled. depending on the i 2 c bus register lbsub different modes are possible (downsample 1, 1.5, 3). as digital 656input data are already in 13.5 mhz format, no downsampling should be used ( lbsub =0). for cvbs, yuv and rgb signals (if dectwo =1) a downsam- pling of 1.5 ( lbsub =2) is required. in principle the input picture is separated in one upper and one lower part. the measurement windows are defined by the parameters lbvwstup , lbv- wendup (upper vertical measurement window), lbvwstlo , lbvwendlo (lower measurement win- dow) and lbhwst , lbhwend (horizontal measure- ment window). a controller software and it s description is available upon request. fig. 2?28: measurement windows zooming parameters lbslaa lbelaa lbformat lbsubtitle lbtoptitle horizontal and/or vertical resizing controller part yuvin yuvout measurement part y hardware (940x) software 4* lbhwend 4* lbhwst 2* lbvwendlo 2* lbvwstlo 2* lbvwendup 2* lbvwstu p
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 21 2.4. output processing 2.4.1. horizontal postscaler after main memory, the display processing is per- formed using a different clock. in this way a decoupling of input and output clocks is achieved. the conversion to the display clock is done by an interpolation filter. this can be used for horizontal expansion in the range of 1...4 in steps of 2 pixels ( hscposc ). due to increased clock frequency in the backend part, the realized horizontal scaling factor depends on backend clock frequency. usually (36 mhz operation), the hori- zontal expansion factors result as 0.75...16. this ensures that the factor 0.75 gives no loss of resolution (to show a 4:3 picture on a 16:9 tube). when using ds656 output, neither horizontal compression nor hor- izontal panorama is possible due to 27 mhz clock. because of the nonlinear characteristic and integer number of pixel, sometimes different hscposc val- ues result in the same decimation factors. fig. 2?29: expansion factor of horizontal postscaler dependent on hscposc 2.4.1.1. panorama mode the picture can be geometrically distorted in horizontal direction for an improved impression in the case of expansions of 4:3 pictures to a 16:9 ratio tube. it is enabled by hpanon . the idea behind this panorama mode is to keep the middle part of the picture in a 4:3 ratio and to stretch the left and the right to fill the entire width of the 16:9 screen. for the adjustment of the expansion process, the picture is divided into 5 seg- ments. for each of these segments the increment value for the expansion factor can be defined sepa- rately. each end of a segment can be defined individu- ally in a granularity of two output pixels. for every seg- ment an increment value can be defined ( hinc0 ... hinc4 ) which indicates the amount of deci- mation/expansion. one lsb is equivalent to an offset of 0.125 to hscpresc per double pixel. this means that with hinc , hscpresc is altered in the range from ? pplop . the first four segments are defined by ( hseg1 ... hseg4 ). the last one goes from hseg4 to pplop. fig. 2?30: visualization of panorama segments table 2?8: horizontal expansion factors hscposc horizontal filter expansion overall expansion clkb36= 27 mhz clkb36= 36 mhz 1024 (min.) 4 4 3 3072 1.33 1.33 1 4095 1 1 0.75 3 0.75 1024 4095 0 1000 2000 3000 4000 0.5 1 1.5 2 2.5 3 3.5 horizontal postscaler hscposc(i2c) overall expansion hscposc (i2c) output pixels hseg1 0 max. inc_val pixels 0 31.875 -32 hinc0 hscale output hseg2 hseg3 hseg4 hinc1 hinc2 hinc3 hinc4 hseg1 0 max. hseg2 hseg3 hseg4 1024 4095 3072 compression expansion
vsp 94x2a data sheet 22 aug. 16, 2004; 6251-552-1ds micronas 2.4.2. operation modes there are four operation modes defined. the first mode is simple aabb, where each stored field in the memory is displayed double times on the tv screen. the second and third mode are aaaa and bbbb, in which only one field phase will be displayed on the tv screen. there is also a fourth mode aaaa mode with | , , freeze command. for the improvement of vcr signals, the chrominance can be shifted one line upwards by chrshft fig. 2?31: explanation of field and display line- scanning pattern table 2?9: examples of panorama mode function panorama extreme pan. lens hscposc 2099 d 1023 d 3999 d hseg1 96 d 96 d 96 d hseg2 192 d 192 d 192 d hseg3 288 d 288 d 288 d hseg4 384 d 384 d 384 d hinc0 40 d 85 d 472 d hinc1 20 d 43 d 492 d hinc2 000 d 000 d 000 d hinc3 492 d 469 d 20 d hinc4 472 d 427 d 40 d applop 960 d 960 d 960 d field b field a odd lines even lines frame/field frame content of picture display line-scanning pattern tv display raster display line-scanning pattern display line-scanning pattern tube, display raster odd lines even lines field ras0 1
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 23 fig. 2?32: 50/60 hz interlaced to 100/120 h z interlaced conversion (aabb) table 2?10: operation modes for scan-rate conversion input field a input field b stopmode scan-rate conversion output field phase 0 output field phase 1 output field phase 2/0 output field phase 3/1 00 aabb mode a n , n n n+1 n+1 n n field opdel read write
vsp 94x2a data sheet 24 aug. 16, 2004; 6251-552-1ds micronas 2.5. display processing the display processing part contains an integrated tri- ple 9-bit dac and performs digital enhancements and manipulations of the digital video component signal. fig. 2?35 shows the block diagram of the display pro- cessing part. 2.5.1. peaking the luminance peaking filter improves the overall fre- quency response of the luminance channel. it consists of two filters working in parallel. they have high pass (hp) and band pass (bp) characteristics. their gain factors are programmable separately ( bcof , hcof ). values greater than 4 peak the signal, whereas values less than 4 attenuate the signal. the high pass and the band pass filters are equipped with a common coring algorithm. it is optimized to achieve a smooth display of grey scales, not to improve the signal-to-noise ratio. therefore no artifacts are produced. coring can be switched off ( ycor ). the fig. 2?34 shows the block diagram of the peaking block. the peaking filter clock frequency is clkb36=36 mhz (27 mhz). the maximum signal frequency of the pic- ture stored in the memory is 6.75 mhz. due to a peak- ing after postscaler, the frequency range of the peak- ing filter varies with the expansion factor of the postscaler. fig. 2?33: peaking filter: bandpass and highpass filter fig. 2?34: block diagram peaking fig. 2?35: block diagram of display processing 0 0.1 0.2 0.3 0.4 0.5 5 0 5 10 15 peaking filter characteristic normalized frequency (b) gain[db] bcof hcof bp hp gainb gainh peak_in peak_out ap coring dac dac dcti ayout auout avout peaking fine delay 4:4:4 delay yin y u v coarse delay dac itu656 encoder 656out cin ycor, hcof, bcof threshc, ascentcti finedel coarsedel shiftuv, dpout656 chromamp pkly, pklu, pklv, 656clk 8 9402/9432 only 8:8:8
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 25 2.5.2. digital color transition improvement (dcti) a digital algorithm is implemented to improve horizon- tal transitions of the chrominance signals resulting in a better picture sharpness. a correction signal propor- tional to the slope of the detected horizontal transition of the input signal is added to the original input signal. the amplitude of the correction signal is adjustable by the i 2 c bus parameter ascentcti . the i2c bus parameter threshc modifies the sensi- tivity of the dcti circuit. high values of threshc result in an improvement of significant color transitions only. table 2?11: conversion table between hcof/bcof and gainhp/gainbp bcof gainbp hcof gainhp 0 ? ? ? ? ? ? ? ? table 2?12: peaking filter adaption for 36 mhz or 27 mhz operation expansion factor of postscaler corresponding frequency of input signal for center frequency bandpass (b=0.25) clkb36=36 mhz/27 mhz corresponding frequency of input signal for center frequency highpass (b=0.5) clkb36=36 mhz/27 mhz 0.75 3.375 mhz / 2.5 mhz 6.75 mhz / 5.06 mhz ... ... ... 1 4.5 mhz / 3.375 mhz 9 mhz / 6.75 mhz ... ... ... 3 13.5 mhz / 10.125 mhz 27 mhz / 20.25 mhz
vsp 94x2a data sheet 26 aug. 16, 2004; 6251-552-1ds micronas 2.5.3. coarse and fine delay before digital-to-analog conversion an adjustment of the phase of the luminance is performed. a coarse delay from ? coarsedel ). finedel shifts the luminance one clkb72 (~14 ns) pixel. this can be used to compensate delays, if the external processing of y and uv produces different delays (e.g. external lowpass filtering). 2.5.4. oversampling and dac after conversion into 8:8:8 format (clkb72=72 mhz), three 9-bit digital-to-analog converters are used for analog yuv output. this twofold-oversampling gener- ates 1920 active pixels per line (when using recom- mended settings) and simplifies the external postfilter- ing. the output voltage is determined by pkly , pklu and pklv and can be set in a range of 0.4 v ...1.9 v (fullscale). 8 bits of the luminance d/a converter are used for the entire signal. the 9th bit is used for over- and under- shoots caused by the peaking to prevent or reduce clipping artifacts. as the cti block seldomly produces such overshoots, a full-scale operation can be acti- vated by chromamp . the output voltages may be calculated by: fig. 2?36: dac output signals 2.5.5. output-sync controller the output sync controller generates horizontal and vertical synchronization si gnals for the scanrate-con- verted output signal. the number of pixels per line is 4* pplop . the default value of 288 results in 1152 pixels/line. with clkb= 36 mhz, the horizontal output frequency is 31.25 khz, which is twice the pal horizontal fre- quency. out of these pixels, 16* applop are displayed as active picture area, which are 960 by default. the position on the screen depends on the napplop . it marks the picture area not active in horizontal direction and moves the active picture in horizontal direction. the number of lines per field is 2* lpfop. this value is only used in the vertical freeruning mode. in vertical locked mode, the number of lines per field is derived from the cvbs signal itself and not adjustable. the active and non-active picture areas are marked by alpfop and nalpfop , respectively. both generators have a so called ?locked-mode? and ?freeruning-mode?. not a ll combinations of these modes make sense. table 2?13 on page 27 shows ingenious configurations. [for unpeaked signals max.] [for peaked signals max.] voltagey 1.56v pkly 256 --------------- ? 0.36v + ?? ?? signaly ? = signaly 160....400 512 ------------------------ = signaly 0....511 512 ------------------ = voltageu v , 1.56v pklu v , 256 ---------------------- - ? 0.36v + ?? ?? chromamp signaluv ? ? = signaluv 128....384 512 ------------------------ = 0 v 16 lsb 240 lsb normal signal range 'black' max. 1.9 v max. 0.9 v pkly 128 lsb upper headroom for peaking 128 lsb lower headroom for peaking 9 bit conversion range 'no color' max. 1.9 v pklu pllv 9 bit conversion range max. 0.95 v chromamp =1 chromamp =0
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 27 fig. 2?37: image format behind memory for freerun mode the backend part works stand alone without analyzing the input signals. the clock domains, input data part and output data part of the ic, are not synchronized to each other. if the output processing works in the freerun mode, the output signals of the osc are generated depending on i 2 c-bus settings. for locked mode the backend part works with a line locked clock. this means that the front-end and the backend of the ic are synchronized to each other. the generation of the controlling signals depend s on output signals from the front-en d. this mode will be the default and the most used mode for standard tv appli- cations. with activated vertical freerun mode the phase of the generated vsync signal has no correlation to the incoming vsync signal. a hard switch from freerun mode to locked mode would therefore cause visible synchronization problems in the deflection unit of the tv set concerning the vertical picture positioning. to avoid these problems a circuit is implemented which synchronizes the freerunning vsync signal to the vsync derived from the cvbs signal, to enable a soft transi- tion to locked mode ( pdgsr , lpfopff ). this syn- chronization is only possible when the number of cvbs input lines corresponds to the programmed value of lpfop . when no or very weak signal is connected to the cvbs input, the ic can be co nfigured to automatically switch into freerunning mo de. this stabilizes the dis- play which may contain osd information, e.g. during channel-tune. the configuration, whether the ic switches to h-freerun, v-freerun or both can be config- ured by autofrrn 2.5.5.1. hout generator the hout generator has two operation modes, which can be selected by the parameter houtfr . the hout signal is active high for 64 clock cycles (clkb36). in the freerunning-mode the hout signal is generated depending on the pplop parameter. in the locked-mode the hout signal is locked on the incom- ing h-sync signal derived from cvbs. the polarity of the hout signal is programmable by the parameter houtpol . 2.5.5.2. vout generator the vout generator has two operation modes, which can be selected by the parameter voutfr . in the fre- erunning-mode ( voutfr =1) the vout signal is gen- erated depending on the lpfop parameter. in the locked-mode the vout signal is synchronized by the incoming v-sync signal derived from cvbs, delayed by some lines ( opdel ). during one incoming v-sync signal, two vout pulses have to be generated. the polarity of the vout signal is programmable by the parameter voutpol . the vout signal is active high for two output lines.. applop (active pixel per line output) hsync nalpfop (not active lines output) alpfop (active lines output) complete picture area pplop lpfop (lines output) (pixel per line output) active picture vsync table 2?13: ingenious configurations of the hout and vout generator mode houtfr voutfr ?h-and-v-locked? mode 0 0 ?h-freerunning / v-locked? mode 1 0 ?h-and v freerunning? mode 1 1
vsp 94x2a data sheet 28 aug. 16, 2004; 6251-552-1ds micronas 2.5.5.3. blank generator the blank signal is used to horizontally and vertically mark active picture area. it is enabled by blanen and its polarity can be chosen by blanpol and vblan- pol . referred to hsync, the start is given by blan- del and its length is given by blanlen , both adjust- able with 4 pixel resolution. referred to vsync, the start is given by vblandel and its length is given by vblanlen , both adjustable in 1 lines resolution. 2.5.5.4. background generator this generator is able to realize an automatic closing and opening of the displayed picture. this means that with every picture the displayed colored background, defined by uborder , vborder and yborder will get bigger or smaller. the original picture data will be replaced by the background values and vice versa. there is also the possibility to realize a fixed border via the i2c bus ( bordposh and bordposv ). 4096 dif- ferent colors are available. bordposh and bordposv also influence the win- dow generation. this means the automatic opening and closing of the picture will start or end at the posi- tion which is defined with these values. the border is calculated with the following formula: the horizontal border on the left side of the tv screen is 2* bord- posh and 2* bordposh on the right side of the tv screen. this means, that 4* bordposh pixels are overwritten with border values. the same applies to the vertical direction. 4* bordposv lines in total are overwritten with background values. borderv decides whether upper or lower or both borders are displayed. borderh decides whether left or right or both borders are displayed. table 2?14: display line scanning pattern sequence display line scanning pattern sequence 1. to 2. 2. to 3. 3. to 4. 4. to 5.(1.) a a a a 312 313 312 313 b b b b 313 312 313 312 a a b b 312 312.5 313 312.5 a b a b 312.5 312.5 312.5 312.5
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 29 2.5.5.5. window function fig. 2?38 shows the functionality of the horizontal win- dow function. the window can be closed or opened. the windowing feature can be enabled by the wind- hon parameter. the windhst and the windhdr parameter determine, what status (opened or closed) the window has, and what can be done with the win- dow (open or close). with each enabling of the window function by the windhon parameter, the status of the window will be as defined by windhst and windhdr . to change from ?close? to ?open? or vice versa only the windhdr parameter has to be tog- gled. the speed of the window can be defined by the windhsp parameter. fig. 2?39 shows the functional- ity of the vertical window function. all settings are also available in vertical direction. all i 2 c parameters exist for both directions (e.g. wind- hon and windvon for horizontal and vertical window enabling). combinations of both window functions (horizontal and vertical) are also possible. fig. 2?38: horizontal windowing fig. 2?39: vertical windowing fig. 2?40: horizontal and vertical windowing close window open window close window open window
vsp 94x2a data sheet 30 aug. 16, 2004; 6251-552-1ds micronas 2.5.6. digital 656 input the ic decodes a digital 8 bit@27 mhz data stream according to itu.bt656 standard. the configuration is set by en_656 . and dpout656 . four input modes are supported: to adjust the input to sources, which deviate from the standard, the field information may be inverted ( f_pol ) and the chrominance format can be chosen between unsigned and 2?s complement format ( cfor- mat ). the polarity of h an v can be inverted by h_pol and v_pol respectively. dependent on ver- sion, the digital input must be selected by ituprtsel (pins i656i or 656io). 2.5.7. digital 656 output dependent on version (single- or double-scan), the output data format corresponds to ccir 656 (8-bit bus at a data rate of 27 mhz) or has double-scan format (8-bit bus at a data rate of 54 mhz). there all frequen- cies and data-rates are doubled compared to standard ccir656 specification. doub le scan format is intended to be used with a suited backend device, e.g. ddp3315c. timing reference codes (sav, eav) are inserted according to the specification. the output can be enabled by dpout656 . the output should be set to 720 pixels per line ( applop ) and the display clock should be set to 27/54 mhz (refer to chapter 2.6. ). the chrominance information can be inverted by chrmsig656 . hout and vout pins may be used in parallel. 2.6. clock concept a single 20.25 mhz crystal at fundamental mode is used as clock reference. all other clocks are derived from this source. the cvbs front-end works with 20.25 mhz, the rgb front-end works with 40.5 mhz, the oversampling dacs use clkb72 and the memory and all parts behind the memory are clocked with clkb36. the frequency of clkb36 and clkb72 is adjustable and depends on application. with analog output, clkb72 is usually 72 mhz and with digital out- put, clkb72 is usually 54 mhz. clkb72 is always twice of clkb36. three different clock concepts are supported. the dif- ference is the behavior in clocking the memory output. the front-end part of the vsp 94x2a uses a freeruning but crystal-stable clock (clkf). after deskewing, an orthogonal picture is written into the memory. the read out is done using the (clkb) clock. the horizontal sync-signal output (hout) is derived from a counter running with clkb. the vout is directly derived from the input vertical signal, which is generated by the sync-separation block. this ? h-fre- erunning-v-locked mode ? is only possible together with a dc coupled deflection controller. in ? h-and-v-locked mode ? clkb is line-locked to the incoming signal. the freerunning yuv picture data and the internal h signal are converted to the line- locked domain. now hout and the sync signal in the 1f h domain are directly coupled. in case of ? h-and-v-freerunning mode ? the hout and vout signals are derived from counters running with clkb. there is no connection to the incoming signal. this mode can be used for stable pictures when no signal is applied (e.g. ch annel search with osd inser- tion). table 2?15: 656 input / output selection en_656 dpout656 656 operation 0 0 input disabled/ output disabled 0 1 input disabled/ output enabled 1 0 input enabled/ output disabled 1 1 input enabled/ output disabled (9412a only) table 2?16: 656 modes imode 656 operation 00 full itu mode (automatic) information about active picture is taken from data-stream 01 full itu mode (manual) information about active picture is taken from applipi , napplipi , alpfipi , nalpfipi 10 itu656 only data, h/v-sync according pa l / n t s c 11 itu656 only data, h/v-sync according itu656
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 31 the selection between freerunning and locked clocks may be forced or selected to be dependent on pll conditions. please refer to fig. 2?41 a clock output of 27 mhz (single-scan version:13.5 mhz) is possible (pin 27: clkout ). this clock is 3/4 of clkb36. hout and vout are in line with this sampling clock. the clock output can be dis- abled by clkouton . additionally a 20.25 mhz clock can be output to pin 74 ( 656hin/clkf20 ) to supply other ics (e.g. pip) with the same clock ( clkf2pad ). when enabled, 656-input with separate h/v-sync is not pos- sible. for 656-output operation, clkb36 is given to pin 9 ( 656clk ). fig. 2?41: conditions for freerunning/locked switching table 2?17: clock system name clock nominal frequency ?h-/v- locked? mode ?h-freerunning- v-locked? mode ?h-/v- freerunning? mode clkf20 cvbs front-end 20.25 mhz fr fr fr clkf40 rgb front-end, input processing 40.5 mhz fr fr fr clkb36 output and dis- play processing 9402: 36 mhz (analog out) 9412: 27 mhz (digital out) ll fr fr clkb72 oversampling, dac 9402: 72 mhz 9412: 54 mhz ll fr fr clkb27 clkout-pin 9402: 27 mhz 9412: 20.25 mhz ll fr fr stab =0 and autofreerun =1x freerun generator ll-pll front-end pll stabll (indicates pll stability) 0 1 0 1 setstabll houtfr 0 1 yes no cvbs clkbxx locked clocks freerunning clocks
vsp 94x2a data sheet 32 aug. 16, 2004; 6251-552-1ds micronas 2.6.1. line-locked clock generator the clock generation system derives all clocks from one 20.25 mhz crystal oscillator clock source. an internal pll multiplies this oscillator frequency by 32, generating a clock of 648 mhz which is used as refer- ence for all clocks needed. line-locked horizontal sync pulses are generated by a digital phase locked loop. the time constant can be adjusted between fast and slow behavior ( kpl, kil ) to accommodate different backend ics. the pll control can be frozen up to 15 lines before v-sync ( fion ) for a duration up to 15 lines ( file ). this may be used to reduce disturbances by h-phase errors which are pro- duced by vcr?s. the output frequency for the 100/120 hz version dependent on iicincr is a freerunning frequency is also generated which may be selected alternatively. the freerunning frequency for the 100/120 hz version dependent on frinc is normally, iicincr and frinc are equal or nearly the same. the value is internally divided by two for the 50/ 60 hz versions. the number of pixels generated by the pll is given by pplip . for line-locked clock generation the following equation must be fulfilled: fig. 2?42: line-locked clock ceneration fig. 2?43: allowed operation area for clock generation f displayll iicincr 103 hz ? = f displayfr frinc 103 hz ? = pplip 2 pplop ? = m u x 648mhz adc phase detector pll 20.25 mhz xtal oscillator sync- separation loop filter ll-dto frequency divider analog cvbs inter- polation iicincr clkf40 clkf20 clkb27 clkb36 clkb72 fr-dto frequency divider frequency divider frinc line-locked locked or freerunning selection nominal 100hz operation (analog out) nominal 50hz operation (analog out) 13.5 / 18 27 / 36 mhz nominal 50hz operation (digital out) nominal 100hz operation (digital out)
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 33 the pll settings for different operation modes can be seen in table 2?18. dependent on input signal (50 hz or 60 hz), the line- locked clock is changing slightly (e.g. from 27 mhz to 27.18 mhz). to have no artifacts when switching between locked and freerun operation, it is possible to change the frinc parameter, after the input tv stan- dard has been detected safely. in case the ic is oper- ating in horizontal locked or freerunning mode only, this adaptivity is not required. table 2?18: recommended ll-pll settings for normal tv-application operation input pplip*4 pplop*4 iicincr frincr clkb36 [mhz] f h [khz] 100/120 hz (analog out) 50 hz 2304 1152 349525 349525 36 31.250 60 hz 351953 36.25 31.468 100/120 hz (digital out) 50 hz 1728 864 262144 262144 27 31.250 60 hz 263892 27.18 31.468 50/60 hz (ana- log out) 50 hz 2304 1152 349525 349525 18 15.625 60 hz 351953 18.125 15.734 50/60 hz (digi- tal out) 50 hz 1728 864 262144 262144 13.5 15.625 60 hz 263892 13.59 15.734
vsp 94x2a data sheet 34 aug. 16, 2004; 6251-552-1ds micronas 3. i 2 c bus interface 3.1. i 2 c bus slave address when pin 19 (adr/tdi) is connected to vss, the vsp 94x2a reacts on the first i 2 c address (b0h for write access and b1h for read access). the second address (b2h and b3h) is active, when pin 19 is con- nected to vdd. 3.1.1. i 2 c bus format the vsp 94x2a i 2 c bus interface acts as a slave receiver and a slave transmitter and provides two dif- ferent access modes (write, read). all modes run with a subaddress auto increment. the interface supports the normal 100 khz transmission speed as well as the high speed 400 khz transmission. the transmitted data is inte rnally stored in registers. the registers are located in four different clock domains. the table 3?5 on page 35 shows the four different clock domains of the vsp 94x2a. the clock domains are called cp - cvbs processing block (20.25 mhz domain, clkf20), fp - front end processing block (40.5 mhz domain, clkf40), bp - back end pro- cessing block (36.0 mhz domain, clkb36) and pp - pll processing block (36.0 mhz domain, clkf36). the registers themselves are grouped in an i 2 c bus interface block, one in each domain. the transmitted data is received by the i 2 c bus kernel. the i 2 c bus ker- nel itself is located in th e cp domain. this means that the working frequency is 20.25 mhz. the data is trans- mitted to the i 2 c bus interface blocks via an internal serial bus. for the write process, the i2c bus master has to write a ?don?t care? byte to th e subaddress ffh (store com- mand). this makes the register values available to the four i2c bus interface blocks (except for the not-take- over registers, which are used immediately). in order to have a defined time step for the several blocks in the different domains, the data are made valid with internal v-syncs, depending on the different clock domains. the subaddresses, where the data are made valid with the v-sync signal of the 20.25 mhz domain are indi- cated in the overview of the subaddresses with ?v20?. the others are called ?v40?, ?v36f? and ?v36b? accordingly. s: start condition sr: repeated start condition a: acknowledge p: stop condition na: not acknowledge table 3?1: i 2 c bus slave addresses b0h and b1h write address1: b0h read address1: b1h 10110000 10110001 table 3?2: i 2 c bus slave addresses b2h and b3h write address2: b2h read address2: b3h 10110010 10110011 table 3?3: write s101100x0a subaddress a data byte a * **** a p table 3?4: read s101100x0a subaddress asr101100x1a data byte a data byte na p
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 35 the i2c parameter v20stat, v40stat and v36bstat reflect the state of the register values. if these bits are read as ?1?, then the store command was sent, but the data is not made available yet. if these bits are ?0? then the data was made valid and a new write or read cycle can start. the bits v20stat , v40stat and v36bstat may be checked before writing or reading new data, otherwise data can be lost by overwriting. no v36fstat register exist. to make the register values available to the four i 2 c bus interface immediately after sending, the i 2 c bus master has to write a ?don?t care? byte to the sub- address feh (store command). for the read process, the i 2 c bus master must not send a store command. in order to have a defined time step for the i 2 c bus interface blocks in the different domains, where the data will be available from the dif- ferent blocks, the data is made valid with the same v- sync related signals mentioned above for the write process. the vsp 94x2a distinguishe s between two different types of read-registers. the behavior of the ?normal? read registers does not differ from the behavior of the write registers. only the direction of the data flow is opposite. the ?rs typ? read registers behave differently. they can be only set (means value 1) by the internal blocks using the rising edge of a corresponding signal. after reading by the i 2 c bus master, the registers will be automatically reset (means value 0) by the i 2 c bus ker- nel/interface. for example the register nmstatus belongs to the ?rs typ? read registers. nmstatus sig- nalizes a new value for noiseme . so if nmstatus is read as ?0? the current noise measurement has not been updated. if the nmstatus is read as ?1? a new noise measurement value can be read. all other ?rs typ? read registers work in the same way. the ?rs typ? read registers will be marked in the overview with the short cut ?rstyp? or will have the additional hint ?note: reset automatically when read/write? in the detailed i 2 c bus command description. by default all registers are made valid by the internal v- sync related signals and, in addition, a store command has to be sent for write registers. the registers, which should also be made available immediately as for writ- ing and reading, are marked with the short cut nto (no take over mechanism). registers which need a hand-shake mechanism between the i 2 c bus interface and the different blocks are marked with the shortcut hs (hand shake mecha- nism). this means that all bits of the registers are used when the last register is writ ten. after pplip9-2 is writ- ten, pplip1-0 must be written to allow these bits to have effect. the registers for the write parameter stopmode are directly connected to the read registers of the parame- ter smmirror . so it is possible to check the i 2 c bus protocol by writing and reading to the register stop- mode and smmirror , respectively. the transmitted data is inte rnally stored in registers. writing to or reading from a non-existant register is permitted and does not generate a fault by the ic. after switching on the ic, all bits of the vsp 94x2a are set to defined states, (refer to table 3?6). por is set after reset to pin 24. it stays ?1?, until it is cancled via software porcncl . this can be used to decide dur- ing tv operation, whether to program all registers (e.g. after power failure reset) or only altered ones (normal tv operation). table 3?5: i 2 c bus clock domains domain description clock cp cp-cd cvbs frontend clkf20 cp-pp ll-pll clkf20 cp-i2c i 2 c read clkf20 fp fp-pre prescaler clkf40 fp-mc memory-controller clkf40 fp-rgb rgb frontend clkf40 fp-tnr temporal noise reduction clkf40 fp-i2c i 2 c read clkf40 pp pp ll-pll clkf36 pp-i2c i 2 c read clkf36 bp bp-dp display processing clkb36 bp-pm pixel-mixer clkb36 bp-odc output data control clkb36 bp-odc/mc output data control/ memory-controller clkb36 bp-pos postscaler clkb36 bp-dac dac processing clkb72 bp-i2c i 2 c read clkb36
vsp 94x2a data sheet 36 aug. 16, 2004; 6251-552-1ds micronas fig. 3?1: i 2 c bus clock domains vsp 94x2a sda scl dac dac dac xout 20,25 mhz 36,0b mhz ayout auout avout hout vout cp (cvbs processing block) bp (back end processing block) xin pp (pll processing block) fp (front end processing block) 72,0 mhz 40,5 mhz o u t 7 2 out 27.0 27,0 mhz 36.0f mhz hprescale tnr rgb m c - 1 m c - 2 odc osc hpostscale picimprove delay i2c cd vin adc agc adc adc cvbs1 cvbso1 s o u r c e s e l e c t fbl/hin2 b/u1 g/y1 r/v1 b/u2 g/y2 r/v2 s o u r c e s e l e c t fbl/hin1 adc adc adc cvbs2 cvbs3 cvbs4 cvbs5 cvbs6 cvbs7 cvbso2 cvbso3 hout50 vout50 table 3?6: i 2 c bus characterization subaddress default r/w take-over subaddress default r/w take-over 00h aah w v40 1dh 44h w v40 01h cah w v40 1eh 00h w v40 02h b0h w v40 1fh ffh w v40 03h c8h w v40 20h 1fh w v40 04h 16h w v40 21h f4h w v40 05h 10h w v40 22h 44h w v40 06h 20h w v40 23h 00h w v40 07h 01h w v40 24h ffh w v40 08h f0h w v40 25h aah w nto 09h 3eh w v40 26h aah w nto 0ah 00h w v40 27h 05h w nto/hs 0bh a0h w v40 28h 00h w nto/rstyp 0ch 00h w v40 29h 60h w nto 0dh 90h w v40 2ah 60h w nto 0eh 80h w v40 2bh 90h w nto 0fh 00h w v40 2ch 00h w nto/hs 10h 20h w v40 2dh 04h w nto
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 37 11h 20h w v40 2eh 00h w nto 12h 00h w v40 2fh 00h w v36b 13h 00h w v40 30h 2dh w v36b 14h 00h w v40 31h 44h w v36b 15h 00h w v40 32h 94h w v36b 16h 00h w v40 33h 20h w v36b 17h 00h w v40 34h 00h w v36b 18h 16h w v40 35h 00h w v36b 19h 00h w v40 36h 01h w v36b 1ah 03h w v40 37h 00h w v36b 1bh 1fh w v40 38h e0h w v36b 1ch f4h w v40 39h 01h w v36b 3ah 00h w v36b 58h 80h w v36b 3bh 00h w v36b 59h 80h w v36b 3ch 26h w v36b 5ah 80h w v36b 3dh 3ch w v36b 5bh 44h w v20 3eh 01h w v36b 5ch 40h w v20 3fh 00h w v36b 5dh c0h w v20 40h 04h w v36b 5eh 5ch w v20 41h 40h w v36b 5fh 66h w v20 42h 20h w v36b 60h 40h w v20 43h 9ch w v36b 61h 40h w v20 44h aah w v36b 62h 00h w v20 45h 00h w v36b 63h 00h w v20 46h 18h w v36b 64h a5h w v20 47h 0bh w v20 65h 5fh w v20 48h 00h w v36b 66h 0fh w v20 49h 00h w v36b 67h 00h w v20 4ah 00h w v36b 68h 00h w v20 4bh 00h w v36b 69h 3ch w v20 4ch 00h w v36b 6ah 03h w v20 table 3?6: i 2 c bus characterization, continued subaddress default r/w take-over subaddress default r/w take-over
vsp 94x2a data sheet 38 aug. 16, 2004; 6251-552-1ds micronas 4dh 00h w v36b 6bh 07h w v20 4eh 55h w v36b 6ch 07h w v20 4fh 0bh w v36b 6dh 1ch w v20 50h 00h w v36b 6eh 5ch w v20 51h 00h w v36b 6fh 00h w v20 52h 00h w v36b 70h 00h w v20 53h 00h w v36b 71h e4h w v20 54h 00h w v36b 72h 00h w v20 55h 00h w v36b 73h 00h w v20 56h 3fh w v36b 74h 00h w v20 57h 3fh w v36b 75h 7fh w v20 76h 00h w v20 b2h 40h w v20 77h 00h w v20 b3h 00h w v20 78h 1ch w v20 b4h ffh w v20 79h 1ch w v20 b5h (no autoincrement) 43h w v20 7ah fch w v20 b6h (spare) 7bh 77h w v20 b7h 00h w v40 7ch 02h w v20 b8h 00h w v40 7dh 6ch w v20 b9h 00h w v40 7eh 00h w v20 bah 00h w v40 7fh 15h w v20 bbh (spare) 80h 00h w v20 bch aah w nto 81h 00h w v20 bdh aah w nto 82h (no autoincrement) 00h w v20 beh 05h w nto 83h r nto bfh (spare) 84h (no autoincrement) rnto c0h 00h wv40 85h r no/rstyp c1h 00h w v40 86-93h r nto d0h 00h w v36 94h-95h (spare) d1h 00h w v36 96h r v40 d2h 00h w v36 97h (spare) e0h 00h w v40 table 3?6: i 2 c bus characterization, continued subaddress default r/w take-over subaddress default r/w take-over
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 39 98h r v36b e1h 00h w v40 99h r v20 e2h 00h w v40 a0h 00h w nto e3h 00h w v40 a1h 00h w nto e4h 00h w v40 a2h ffh w nto e5h 00h w v40 a3h ffh w nto e6h 00h w v40 a4h 00h w nto e7h 00h w v40 b0h 10h w v20 e8h 00h w v40 b1h 00h w v20 e9h 00h w v40 eah 00h w v40 ebh 00h w v40 ech 00h w v40 edh 00h w v40 eeh 00h w v40 efh 00h w v40 f0-f6h r nto f7h-fdh (spare) feh w ffh w take-over mechanism register types nto no take-over mechanism w write register v20 take-over with v-sync in 20 mhz domain r read register v40 take-over with v-sync in 40 mhz domain rrstyp reset register after reading v36b take-over with v-sync in back-end 36.0 mhz domain hs handshake mechanism required table 3?6: i 2 c bus characterization, continued subaddress default r/w take-over subaddress default r/w take-over
vsp 94x2a data sheet 40 aug. 16, 2004; 6251-552-1ds micronas 3.1.2. i 2 c bus list in alphabetical order name subaddress aabyp 0ch accfix 5bh accfrz 5bh acclim 7ah adcsel 0ch adlck 81h adlckcc 81h adlcksel 81h afproc 4dh agcadj1 67h agcadj2 68h agcadjb 16h agcadjcv 90h agcadjf 17h agcadjg 15h agcadjr 14h agcfrze 68h agcmd 67h agcres 68h agcthd b0h alpfip 05h alpfipi b8h alpfop 32h am50o 90h am60o 90h amstd50 b1h amstd60 b1h apensel 05h applip 01h applipi b9h applop 3dh ascentcti 30h autofrrn 32h bcof 31h bellfir 7dh belliir 7dh bgpos 47h blandel 07h blanen 36h blanlen 08h blanpol 36h borderh 45h borderv 45h bordposh 35h bordposv 34h brtadj 0ah cdelhpos 4fh cformat 18h chrf 5eh chrmsig656 55h chromamp 57h chromsign 57h chrsf 0bh chrshft 3dh ckill 60h ckills 61h ckstat 88h clkf2pad 16h clkoutinv 4fh clkouton 30h clkoutsel 4fh clkoutsel72 4dh clkt 2eh clmpd1 6bh clmpd1s 7bh clmpd2 6ch clmpd2s 7bh name subaddress
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 41 clmphigh 69h clmplow 6ah clmpst1 6dh clmpst1s 78h clmpst2 6eh clmpst2s 79h clmpvg 10h clmpvrb 0dh clpstgy 6bh clrange 5dh coarsedel 32h colon 5bh comb 5fh con 5ch conadj 0bh cons 5bh cpllof 82h cpllres 80h crcb 5bh cstand 5fh cvbosel1 6ah cvbosel2 70h cvbosel3 70h cvbsel1 6fh cvbsel2 6fh dclmpf 10h dectwo 0bh deempfir b5h deempiir b5h deempstd 82h dethpol 88h detvpol 88h disallres 80h dischch 6ch name subaddress disres 27h dpout656 56h eia770 7ch en_656 18h enlim 7eh f_pol 18h fblactive 83h fblconf 0dh fbldel 0dh fbloffst 0ch femag b1h fhdet 6ch fhfrrn 71h fieldbinv 54h file 2eh finedel 32h fioffoff 54h fion 2dh fkoi 2ch fkoihys 2ch fldinv 6bh fline 6bh flnstrd 7eh fmod 29h foffst c1h freeze 3fh freqsel 7ch frfix 1ah frinc bch fswftl d0h gofst 0eh gradelaa f3h gradisstable f2h h_pol 18h name subaddress
vsp 94x2a data sheet 42 aug. 16, 2004; 6251-552-1ds micronas haapresc 09h hcof 31h hdcpresc 05h hdtotest 2eh hinc0 48h hinc1 49h hinc2 4ah hinc3 4bh hinc4 4ch hincrext 29h hinp 6dh horpos 3ah horwidth 38h houtdel 3eh houtfr 41h houtpol 41h hpanon 4fh hpol 6ch hres 28h hscposc 4eh hscpresc 01h hseg1 50h hseg2 51h hseg3 52h hseg4 53h hsppl c0h hswin 29h htestw 2ah hue 63h hwid 2eh ifcomp 7ah ifcomstr 82h iicincr 25h imode 18h name subaddress int 89h ishft 7eh ituprtsel 16h kd2 29h kil a1h kinl a1h koih 2ah koiwid 2ah kpl a0h kpnl a0h lb43sens e9h lbactivity ech lbasdel efh lbelaa f0h lbformat f2h lbfs e6h lbgfbdel edh lbgraddet e0h lbgradrst eah lbgsdel eeh lbhistbla e4h lbhiwhite e3h lbhsdel eah lbhwend e2h lbhwst e7h lbngfen e9h lbslaa f0h lbstability e9h lbstatus 85h lbsub eah lbsubtitle f2h lbthdnbng e9h lbthdnbnha ebh lbtoptitle f2h name subaddress
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 43 lbvwendlo e1h lbvwendup e6h lbvwstlo e5h lbvwstup e8h limen 2ch limii a3h limip a2h limlr a4h lmod 29h lmofst 5dh lnl 2dh lnstdrd 89h locksp 47h lpblack f5h lpcdel 72h lpfipmd 2fh lpfld 8ah lpfop 43h lpfopff 3ch lppost 62h lpwhite f5h minv 92h mixgain 0fh mixop 0dh mll 09h mvp b2h mvpg b2h nalpfip 04h nalpfipi bah nalpfop 45h napipphi 17h napplip 02h napplipi b7h napplop 3fh name subaddress nmline 19h nmpos 1ah nmsense 1ah nmstatus 85h nogradfound f2h noiseme 84h nosigb 6dh nosync 3ch notchoff 5ch nron 1ah nrpixel 8bh nsred 72h/7eh ntchsel 80h ntscref 64h opdel 44h oscpd 7ch pa l d e l 4 7 h pa l d e t 8 c h palid 88h palidl0 75h palidl1 74h palidl2 82h palinc1 82h palinc2 82h pa l r e f 6 5 h pb 85h pdgsr 3fh pfbl 85h pg 85h pklu 59h pklv 5ah pkly 58h plltc 6eh por 8ch name subaddress
vsp 94x2a data sheet 44 aug. 16, 2004; 6251-552-1ds micronas porcncl 80h pplip 2bh pploff 3ch pplop 41h pr 85h pwadjcnt 93h pwthd 5dh rbofst 0eh rdctrldis 45h refron 41h refrper 41h reftrim 76h reftrimcv 77h reftrimcvrd 8eh reftrimen 72h reftrimrd 8dh reftrimrgb 77h reftrimrgbrd 8eh rev f6h rgbsel 0fh satnr 72h scadj 66h scdev 89h scmidl 79h scmrel 7fh scouten 88h sdb b2h sdr 5eh secacc 7fh secaccl 81h secdiv 7fh secinc1 7fh secinc2 7fh secntch 5ch name subaddress setstabll 2ch shaperdis 7ch shiftuv 56h skewsel 0eh sllthd 66h sllthdv b1h sllthdvp 78h sls 8fh/f6h smmirror 87h smop 0eh stab 8ch stabll 86h standby 11h stdet 88h stopmode 3fh subtitle f2h switchto43 f2h synfthd 82h threshc 30h thrsel 78h tnrabs 1ah tnrclc 24h tnrcly 24h tnrs0c 20h tnrs0y 1bh tnrs1c 20h tnrs1y 1bh tnrs2c 21h tnrs2y 1ch tnrs3c 21h tnrs3y 1ch tnrs4c 22h tnrs4y 1dh tnrs5c 22h name subaddress
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 45 tnrs5y 1dh tnrs6c 23h tnrs6y 1eh tnrs7c 23h tnrs7y 1eh tnrsel 1ah tnrssc 1fh tnrssy 1fh toptitle f2h trapblu 80h trapred 80h tstshaperi 7ch uborder 37h upblack f5h upwhite f5h usatadj 10h uvcor 5ch uvdel 13h v_pol 18h v20stat 99h v36bstat 98h v40stat 96h v656del 4dh vblandel d0h vblanlen d0h vblanpol d0h vborder 37h vdel_en 55h vdelf_en 03h vdetifs 5dh vdetitc b2h version 8fh/f6h vflymd 8ch vflywhl 7dh name subaddress vflywhlmd 81h vinmthd 2fh vinp 72h vlength 91h vlp 7eh voutfr 41h voutpol 41h vpol 62h vsatadj 11h vshift 73h vsignal 18h vslpf c1h vthrh50 75h vthrh60 b4h vthrl50 74h vthrl60 b3h windhdr 3bh windhon 3bh windhsp 3bh windhst 3bh windvdr 39h windvon 39h windvsp 39h windvst 39h wrctrldis 09h y2rgb 12h yborder 36h ycdel 62h ycor 30h ycsel 6bh yfdel 12h yuvsel 0eh name subaddress
vsp 94x2a data sheet 46 aug. 16, 2004; 6251-552-1ds micronas 3.1.3. i 2 c bus command table table 3?7: i 2 c register overview sub add (hex) data byte d7 d6 d5 d4 d3 d2 d1 d0 input processing 00h applip[8:1] 01h applip[0] hscpresc [11:5] 02h hscpresc[4:0] napplip[9:7] 03h vdelf_en napplip6[6:0] 04h nalpfip 05h apensel nalpfip8 alpfip[9:8] hdcpresc 06h alpfip[7:0] 07h blandel 08h blanlen 09h wrctrldis haapresc mll rgb front-end 0ah brtadj 0bh dectwo chrsf conadj 0ch adcsel aabyp fbloffst 0dh clmpvrb1 clmpvrb0 fbldel mixop fblconf 0eh yuvsel smop skewsel rbofst gofst 0fh rgbsel mixgain 10h clmpvg dclmpf usatadj 11h standby1 standby0 vsatadj 12h y2rgb yfdel 13h uvdel 14h agcadjr 15h agcadjg 16h ituprtsel clkf2pad agcadjb 17h napipphi1 napipphi0 agcadjf 18h imode vsignal cformat f_pol h_pol v_pol en_656 noise reduction 19h nmline [7:0] 1ah nmpos nmsense nmline [8] tnrabs nron tnrsel 1bh tnrs0y tnrs1y 1ch tnrs2y tnrs3y 1dh tnrs4y tnrs5y 1eh tnrs6y tnrs7y 1fh tnrssy tnrssc
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 47 20h tnrs0c tnrs1c 21h tnrs2c tnrs3c 22h tnrs4c tnrs5c 23h tnrs6c tnrs7c 24h tnrcly tnrclc line-locked clock pll 25h iicincr[18:11] 26h iicincr[10:3] 27h disres iicincr[2:0] 28h hres 29h hswin kd2 hincrext lmod fmod 2ah koiwid koih htestw 2bh pplip[9:2] 2ch setstabll frfix limen fkoi fkoihys pplip[1:0] 2dh fion lnl 2eh clkt hwid hdtotest file 2fh lpfipmd vinmthd display processing 30h ycor clkouton threshc ascentcti 31h hcof bcof 32h autofrrn alpfop[9:8] finedel coarsedel 33h alpfop[7:0] 34h bordposv 35h bordposh [7:0] 36h blanpol blanen bordposh[9:8] yborder 37h uborder vborder 38h horwidth[7:0] 39h windvsp windvst windvdr windvon horwidth[10:8] 3ah horpos 3bh windhsp1 windhsp0 windhst wi ndhdr windhon horpos[10:8] 3ch nosync pploff lpfopff 3dh chrshft applop 3eh houtdel 3fh napplop[9:8] pdgsr freeze stopmode houtdel[9:8] 40h napplop 41h pplop[9:8] refrper refron houtpol voutpol houtfr voutfr 42h pplop[7:0] 43h lpfop table 3?7: i 2 c register overview, continued sub add (hex) data byte d7 d6 d5 d4 d3 d2 d1 d0
vsp 94x2a data sheet 48 aug. 16, 2004; 6251-552-1ds micronas 44h opdel[7:0] 45h borderv borderh rdctrldis lpfop8 nalpfop8 opdel[8] 46h nalpfop panorama scaler 47h paldel.1 paldel.0 locksp bgpos 48h hinc0 [7:0] 49h hinc1 [7:0] 4ah hinc2 [7:0] 4bh hinc3 [7:0] 4ch hinc4 [7:0] 4dh v656del afproc clkoutsel272 hinc4 [8] hinc3 [8] hinc2 [8] hinc1 [8] hinc0 [8] 4eh hscposc [7:0] 4fh cdelhpos clkoutsel clkoutinv hpanon hscposc [11:8] 50h hseg1 51h hseg2 52h hseg3 53h hseg4 54h fioffoff fieldbinv hseg2 [10:8] hseg1 [10:8] 55h chrmsig656 vdel_en hse g4 [10:8] hseg3 [10:8] dac control 56h shiftuv dpout656 57h chromsign chromamp 58h pkly 59h pklu 5ah pklv cvbs front-end 5bh cons colon crcb accfix accfrz 5ch con uvcor notchoff secntch 5dh pwthd clrange lmofst vdetifs 5eh sdr chrf 5fh comb cstand 60h ckill 61h ckills 62h vpol lppost ycdel 63h hue 64h ntscref 65h palref 66h sllthd scadj table 3?7: i 2 c register overview, continued sub add (hex) data byte d7 d6 d5 d4 d3 d2 d1 d0
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 49 67h agcmd agcadj1 68h agcres agcfrze agcadj2 69h clmphigh 6ah cvbosel1 clmplow 6bh fline fldinv cl pstgy ycsel clmpd1 6ch hpol1 hpol0 fhdet dischch clmpd2 6dh nosigb hinp clmpst1 6eh plltc clmpst2 6fh cvbsel2 cvbsel1 70h cvbosel2 cvbosel3 71h fhfrrn 72h reftrimen satnr vinp nsred lpcdel 73h vshift 74h palidl1 vthrl50 75h palidl0 vthrh50 76h reftrim 77h reftrimcv reftrimrgb 78h sllthdvp thrsel clmpst1s 79h scmidl clmpst2s 7ah acclim ifcomp 7bh clmpd2s clmpd1s 7ch eia770 shaperdis oscpd tstshaperi freqsel1 freqsel0 7dh bellfir belliir vflywhl 7eh flnstrd enlim ishft nsred2 vlp 7fh secacc secdiv secinc1 secinc2 scmrel 80h porcncl ntchsel cpllres disallres trapblu trapred 81h adlck adlcksel adlckcc vflywhlmd secaccl 82h synfthd ifcomstr palidl2 cpllof deempstd palinc1 palinc2 read register 83h fblactive 84h noiseme 85h lbstatus pfbl pg pb pr nmstatus 86h stabll 87h smmirror 88h dethpol detvpol stdet scouten palid ckstat 89h lnstdrd int scdev 8ah lpfld 8bh nrpixel table 3?7: i 2 c register overview, continued sub add (hex) data byte d7 d6 d5 d4 d3 d2 d1 d0
vsp 94x2a data sheet 50 aug. 16, 2004; 6251-552-1ds micronas 8ch por vflymd stab pa l d e t 8dh reftrimrd 8eh reftrimcvrd reftrimrgbrd 8fh sls version 90h am50o am60o agcadjcv 91h vlength 92h minv 93h pwadjcnt 96h v40stat 97h 98h v36bstat 99h v20stat pp a0h kpnl[3:0] kpl[3:0] a1h kinl[3:0] kil[3:0] a2h limip a3h limii a4h kpnl[4] kpl[4] kinl[4] kil[4] limlr cvbs front-end b0h agcthd femag b1h sllthdv amstd60 amstd50 b2h sdb mvpg mvp vdetitc b3h vthrl60 b4h vthrh60 b5h deempiir deempfir itu input b7h napplipi b8h alpfipi b9h applipi [7:0] bah applipi[8] nalpfipi ll-pll bch frinc[18:11] bdh frinc[10:3] beh frinc[2:0] c0h hsppl c1h foffst vslpf table 3?7: i 2 c register overview, continued sub add (hex) data byte d7 d6 d5 d4 d3 d2 d1 d0
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 51 d0h vblandel [9:8] vblanpol fswftl vblanlen [9:8] d1h vblandel [7:0] d2h vblanlen [7:0] letterbox detection e0h lbgraddet e1h lbvwendlo e2h lbhwend e3h lbhiwhite e4h lbhistbla e5h lbmasla lbvwstlo e6h lbfs lbvwendup e7h lbvisuon lbhwst e8h lbvwstup e9h lbstability lb43sens lbngfen lbthdnbng eah lbsub1 lbsub0 lbgradrst lbhsdel ebh lbthdnbnha ech lbactivity edh lbgfbdel eeh lbgsdel efh lbasdel letterbox read f0h lbslaa f1h lbelaa f2h lbformat lbsubtitle lbtopt itle gradisstable toptitle subtitle nogradfound switchto43 f3h gradelaa[8] gradslaa f4h gradelaa[7:0] f5h lpblack upblack lpwhite upwhite f6h version sls rev feh take-over-indication (immediately) ffh take-over-indication (after v-pulse) table 3?7: i 2 c register overview, continued sub add (hex) data byte d7 d6 d5 d4 d3 d2 d1 d0
vsp 94x2a data sheet 52 aug. 16, 2004; 6251-552-1ds micronas 3.1.4. i 2 c bus command description underlined values are initialized at power-on. some bits are intended to not be user adjustable. mandatory and recommended settings are available from micro- nas in a separate document (application note: i 2 c settings). table 3?8: i 2 c bus command description bit name description subaddress 00h d7-d0 applip8-1 [fp-pre] active pixel per line number of pixels to be stored in memory granularity: 2 pixel ?000000000?: 0 pixel ?101010101?: 682 pixel ?111111111?: 1022 pixel subaddress 01h d7 applip0 [fp-pre] belongs to 00h d6-d0 hscpresc11-5 [fp-pre] control signal for hscale in horizontal pre-scaler ?000000000000?: subsampling factor by scaler stage is 1 ?100000000000?: subsampling factor is 1.5 (720 pixel) ?100101010110?: subsampling factor is 1.583 (682 pixel) ?111111111111?: subsampling factor is 2 (540 pixel) subaddress 02h d7-d3 hscpresc4-0 [fp-pre] belongs to 01h d2-d0 napplip9-7 [fp-pre] not active pixel per line granularity: 2 clock cycles (~50 ns) ?0000000000?: 0 clock cycles ?0001001000?: 144 clock cycles (~7.2 subaddress 03h d7 vdelf_en [fp-pre] vertical pulse delay frontend ?0?: no delay ?1?: delayed d6-d0 napplip6-0 [fp-pre] belongs to 02h subaddress 04h d7-d0 nalpfip7-0 [fp-pre] not active lines per field (input processing) ?000000000?: 0 lines ?000010110?: 22 lines ?111111111?: 511 lines
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 53 subaddress 05h d7 apensel [fp-pre] active pixel enable select 0: count clock cycles (recommended for cvbs/rgb input) 1: count active pixels (recommended for itu656 input) d6 nalpfip8 [fp-pre] belongs to 04h d5-d4 alpfip9-8 [fp-pre] active lines per field ?0000000000?: no active line ?0100100000?: 288 active lines ?1111111111?: 1023 active lines d3-d0 hdcpresc horizontal pre-scaler decimates by ?0000?: 1 ?0001?: 2 ?0010?: 3 ?0011?: 4 ?0100?: 6 ?0101?: 8 ?0110?: 12 ?0111?: 16 ?1000?: 24 ?1001?: 32 subaddress 06h d7-d0 alpfip7-0 belongs to 05h subaddress 07h d7-d0 blandel blanking signal delay delay in pixels from hsync to active edge of blank signal: blank_start=4* blandel ?00000000?: no delay ?00000001?: 4 pixel delay ?11111111?: 1020 pixel delay subaddress 08h d7-d0 blanlen blanking signal length length in pixels from start of active blank signal: blank_length=4* blanlen ?00000000?: no pixel ?11110000?: 960 pixel ?11111111?: 1020 pixel length table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 54 aug. 16, 2004; 6251-552-1ds micronas subaddress 09h d6 wrctrldis [fp-mc] memory write control circuit disable ?0?: enabled ?1?: disabled d5-d4 haapresc [fp-mc] horizontal anti alias filter ?00?: filter bypassed ?01?: force characteristic weak ?10?: force characteristic strong ?11?: automatic characteristic (weak or strong) note: for normal cvbs/rgb full-screen, f ilter should be set to weak or auto- matic characteristic. for itu656 full-screen input, filter should be bypassed. strong characteristic is fo r split-screen and pip only. d3-d0 mll [fp-mc] minimum line length effective number of clock periods: 600 + mll*128 1110: corresponds to 2392 clock periods subaddress 0ah d7-d0 brtadj [fp-rgb] brightness adjustment of rgb/yuv input ?10000000?: ? subaddress 0bh d7 dectwo [fp-rgb] decimation by 2 decimation of rgb/yuv signal before soft-mix ?0?: no decimation ?1?: decimation by 2 d6 chrsf [fp-rgb] additional chroma subsampling filter ?0?: disabled ?1?: enabled d5-d0 conadj [fp-rgb] contrast adjustment of rgb/yuv input ?000000?: 0 ?000001?: 1/32 ?100000?: 1 ?111111?: 63/32 subaddress 0ch d7 adcsel [fp-rgb] select adc for sync signal conversion ?0?: use adc_g ?1?: use adc_fbl d6 aabyp [fp-rgb] bypass rgb/yuv antialiasfilter ?0?: use filter ?1?: bypass d5-d0 fbloffst [fp-rgb] fast blank offset correction ?000000?: 0 lsb offset ?111111?: 63 lsb offset table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 55 subaddress 0dh d7-d6 clmpvrb [fp-rgb] clamping value red and blue adc ?00?: 16 (b/r signal without sync) ?01?: 80 (b/r signal with sync) ?10?: 128 (u/v signal) ?11?: (reserved) d5-d3 fbldel [fp-rgb] fast blank delay vs. rgb/yuv input granularity: 25 ns ?000?: ? mixing configuration ?00?: enable soft-mix ?01?: only rgb path visible ?10?: only cvbs path visible ?11?: (reserved) d0 fblconf [fp-rgb] configuration of fblactive signal ?0?: react after one clock (25 ns) active fbl input ?1?: react after 5 clock (125 ns) active fbl input subaddress 0eh d7 yuvsel [fp-rgb] yuv or rgb input selection ?0?: yuv expected ?1?: rgb expected d6 smop [fp-rgb] softmix operation mode ?0?: dynamic ?1?: static d5 skewsel [fp-rgb] skew correction for rgb/yuv channel ?0?: skew correction enabled ?1?: skew correction disabled (for pip3, pip4 only) d4-d2 rbofst [fp-rgb] clamping correction for r/b adc ?000?: 0 (r/b, no pedestal offset visible) ?001?: 16 ?010?: 64 (r/b with sync, no pedestal offset visible) ?011?: 80 ?100?: 127 (uv negative pedestal offset) ?101?: 128 (uv) ?110?: 129 (uv positive pedestal offset) ?111?: (reserved) d1-d0 gofst [fp-rgb] clamping correction for g adc ?00?: 0 (g/y, no pedestal offset visible) ?01?: 16 ?10?: 64 (g/y with sync, no pedestal offset visible) ?11?: 80 table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 56 aug. 16, 2004; 6251-552-1ds micronas subaddress 0fh d7 rgbsel [fp-rgb] input selection ?0?: use rgb/yuv input1 ?1?: use rgb/yuv input2 d6-d0 mixgain [fp-rgb] gain of fast blank signal ?1000000?: ? note: for proper operation in dynamic softmix mode, absolute value of mix- gain must be bigger than 2 (e.g. 3) subaddress 10h d7 clmpvg [fp-rgb] clamping value g adc ?0?: 16 ?1?: 80 d6 dclmpf [fp-rgb] clamping fast blank input ?0?: enable clamping ?1?: disable clamping (dc coupling) d5-d0 usatadj [fp-rgb] u saturation adjustment ?000000?: 0 ?000001?: 1/32 ?100000?: 1 ?111111?: 63/32 subaddress 11h d7-d6 standby [fp-rgb] standby mode ?00?: all analog cores active ?01?: rgb/fbl adcs in stand-by mode ?10?: rgb/fbl and cvbs adcs and dacs in stand-by mode ?11?: dacs in stand-by mode d5-d0 vsatadj [fp-rgb] v saturation adjustment ?000000?: 0 ?000001?: 1/32 ?100000?: 1 ?111111?: 63/32 subaddress 12h d7 y2rgb [fp-rgb] y to rgb (for yuv mode) 0: use y from green adc 1: use y from cvbs adc d5-d0 yfdel [fp-rgb] y/fbl delay adjustment granularity: 50 ns ?000000?: no delay ?111111?: 3.15 table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 57 subaddress 13h d5-d0 uvdel [fp-rgb] uv delay adjustment granularity: 50 ns ?000000?: no delay ?111111?: 3.15 subaddress 14h d5-d0 agcadjr [fp-rgb] conversion range adjustment red ?000000?: 0.5 v input signal ?111111?: 1.5 v input signal subaddress 15h d5-d0 agcadjg [fp-rgb] conversion range adjustment green ?000000?: 0.5 v input signal ?111111?: 1.5 v input signal subaddress 16h d7 ituprtsel [fp-rgb] itu port selection 0: first input (656io) 1: second input (i656i) d6 clkf2pad [fp-rgb] frontend clock is given to pin 74 ?0? pin 74 is used as h-input for itu656 ?1?: clkf20 (20.25 mhz) is given to pin 74 d5-d0 agcadjb [fp-rgb] conversion range adjustment blue ?000000?: 0.5 v input signal ?111111?: 1.5 v input signal subaddress 17h d7-d6 napipphi [fp-rgb] cbycry-phase shift ?0?: no phase shift d5-d0 agcadjf [fp-rgb] conversion range adjustment fast blank ?000000?: 0.5 v input signal ?111111?: 1.5 v input signal table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 58 aug. 16, 2004; 6251-552-1ds micronas subaddress 18h d7-d6 imode [fp-rgb] input format ?00?: full itu mode (automatic) ?01?: full itu mode (manual) ?10?: itu656 only data, h/v-sync according pal/ntsc ?11?: itu656 only data, h/v-sync according itu656 d5 vsignal [fp-rgb] input signal ?0?: interlaced ?1?: non interlaced d4 cformat [fp-rgb] chrominance data format ?0?: unsigned ?1?: 2s complement d3 f_pol [fp-rgb] field polarity ?0?: field a=0, field b=1 ?1?: field a=1, field b=0 d2 h_pol [fp-rgb] h656 polarity ?0?: h656 active low ?1?: h656 active high d1 v_pol [fp-rgb] v656 polarity ?0?: v656 active low ?1?: v656 active high d0 en_656 [fp-rgb] itu656-input interface ?0?: analog input enabled (cvbs/rgb) ?1?: itui enabled subaddress 19h d7-d0 nmline7-0 [fp-tnr] line for noise measurement 0 d : line 2 1 d : line 3 311 d : line 1 (pal) 261 d : line 1 (ntsc) lines 3-260 are not standard dependent table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 59 subaddress 1ah d7-d6 nmpos [fp-tnr] noise measurement analyze window position 00: 6.3 noise measurement sensitivity 00: *1 01: *2 10: *4 11: *8 d3 nmline8 [fp-tnr] belongs to 19h d2 tnrabs [fp-tnr] motion detector works on absolute values: ?0?: absolute values not calculated ?1?: absolute values calculated d1 nron [fp-tnr] temporal noise reduction ?0?: disabled ?1?: enabled d0 tnrsel [fp-tnr] chrominance motion values from: ?0?: luminance motion detector ?1?: separate chrominance motion detector subaddress 1bh d7-d4 tnrs0y [fp-tnr] tnr curve characteristic of luma segment 0 default value: 0001 d3-d0 tnrs1y [fp-tnr] tnr curve characteristic of luma segment 1 default value: 1111 subaddress 1ch d7-d4 tnrs2y [fp-tnr] tnr curve characteristic of luma segment 2 default value: 1111 d3-d0 tnrs3y [fp-tnr] tnr curve characteristic of luma segment 3 default value: 0100 subaddress 1dh d7-d4 tnrs4y [fp-tnr] tnr curve characteristic of luma segment 4 default value: 0100 d3-d0 tnrs5y [fp-tnr] tnr curve characteristic of luma segment 5 default value: 0100 subaddress 1eh d7-d4 tnrs6y [fp-tnr] tnr curve characteristic of luma segment 6 default value: 0000 d3-d0 tnrs7y [fp-tnr] tnr curve characteristic of luma segment 7 default value: 0000 table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 60 aug. 16, 2004; 6251-552-1ds micronas subaddress 1fh d7-d4 tnrssy [fp-tnr] tnr start value of luma lut default value: 1111 d3-d0 tnrssc [fp-tnr] tnr start value of chroma lut default value: 1111 subaddress 20h d7-d4 tnrs0c [fp-tnr] tnr curve characteristic of chroma segment 0 default value: 0001 d3-d0 tnrs1c [fp-tnr] tnr curve characteristic of chroma segment 1 default value: 1111 subaddress 21h d7-d4 tnrs2c [fp-tnr] tnr curve characteristic of chroma segment 2 default value: 1111 d3-d0 tnrs3c [fp-tnr] tnr curve characteristic of chroma segment 3 default value: 0100 subaddress 22h d7-d4 tnrs4c [fp-tnr] tnr curve characteristic of chroma segment 4 default value: 0100 d3-d0 tnrs5c [fp-tnr] tnr curve characteristic of chroma segment 5 default value: 0100 subaddress 23h d7-d4 tnrs6c [fp-tnr] tnr curve characteristic of chroma segment 6 default value: 0000 d3-d0 tnrs7c [fp-tnr] tnr curve characteristic of chroma segment 7 default value: 0000 subaddress 24h d7-d4 tnrcly [fp-tnr] tnr luminance classification ?0000?: strong noise reduction ?1111?: slight noise reduction d3-d0 tnrclc [fp-tnr] tnr chrominance classification ?0000?: strong noise reduction ?1111?: slight noise reduction subaddress 25h d7-d0 iicincr18-11 [pp] set hdto frequency granularity=103 hz 33981 d (minimum: nominal pixel clock= 3.5 mhz) 349525 d (nominal pixel clock= 36 mhz) 388362 d (maximum: nominal pixel clock= 40 mhz) table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 61 subaddress 26h d7-d0 iicincr10-3 [pp] belongs to 25h subaddress 27h d3 disres [pp] reset of ll-pll watchdog ?0?: reset disabled ?1?: reset enabled d2-d0 iicincr2-0 [pp] belongs to 25h subaddress 28h d0 hres [pp] reset of ll-hpll ?0?: no reset ?1?: reset note: reset automatic ally when written subaddress 29h d7-d4 hswin [pp] width of noise suppression window of ll-hpll ?0000?: phase detector steepness ?0?: steepness for normal tv operation mode ?1?: steepness for operations where pplip is less than 288 d d2 hincrext [pp] hdto testmode ?0?: normal mode ?1?: line-locked-clocks derived from frontend line-length d1 lmod [pp] selects line locked mode ?0?: line locked-clocks derived from hpll ?1?: line-locked-clocks derived from frontend line-length d0 fmod [pp] selects freerun mode ?0?: freerun-clocks derived from crystal ?1?: freerun-clocks derived from hdto adjustable frequency is only possible when set to ?1?. when set to ?0?, backend clock is always 36 mhz (9432/42: 18 mhz) table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 62 aug. 16, 2004; 6251-552-1ds micronas subaddress 2ah d7-d6 koiwid [pp] window-width of coincidence detector ?00?: hysteresis of coincidence detector ?00?: 0 lines ?01?: 8 lines ?10?: 16 lines ?11?: 32 lines d3-d0 htestw [pp] test bits for hpll 00: default subaddress 2bh d7-d0 pplip9-2 [pp] pixel per line input (input-processing) granularity=4 pixel ?175 d ?: 700 (minimum) ?576 d ?: 2304 ?963 d ?: 3852 (maximum) subaddress 2ch d7 setstabll [pp] stability signal of ll_hpll ?0?: stabll is generated by the hpll ?1?: stabll is forced to 1 d6 frfix [pp] freerunning clocks ?0?: from fixed clock divider ?1?: from freerunning dto (adjustable clocks) d4 limen [pp] limiter enable ?0?: a32 behavior for limip and limii ?1?: normal limii and limip characteristic d3 fkoi [pp] force coincidence bit ?0?: coincidence bit dynamically changed ?1?: coincidence bit forced to 1 d2 fkoihys [pp] force coincidence hysteresis bit ?0?: coincidence hysteresis bit dynamically changed ?1?: coincidence hysteresis bit forced to 1 d1-d0 pplip1-0 [pp] belongs to 2bh subaddress 2dh d7-d4 fion [pp] increment freeze before v-sync ?0?: no freeze ?15?: freeze starts 15 lines before v-sync d0 lnl [pp] dynamic time constant control ?0?: linear mode ?1?: non linear mode table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 63 subaddress 2eh d7-d6 clkt [pp] switch clkf20 and clkf40 to pads cvbs1 or bin2 (test only) ?00?: no clock ?01?: cvbs1 is output of clkf40 ?10?: bin2 is output of clkf20 ?11?: cvbs1 is output of clkf40 and bin2 is output of clkf20 d5 hwid [pp] minimum width of h-sync ?0?: 60*t clkllf36 ?1?: 15*t clkllf36 d4 hdtotest [pp] test-bit for hpll ?0?: normal mode ?1?: test mode d3-d0 file [pp] increment freeze duration ?0?: no freeze ?15?: increment is frozen for 15 lines subaddress 2f d1 lpfipmd [bp-dp] lines per field method 0: backend 1: frontend d0 vinmthd [bp-dp] vertical odc line counting 0: field delay 1: frame delay subaddress 30h d7-d6 ycor [bp-dp] luminance coring ?00?: off ?01?: 2 ?10?: 4 ?11?: 8 d5 clkouton [bp-dp] clkout pad: ?0?: off (tristate) ?1?: on d4-d2 threshc [bp-dp] slope of dcti function ?000?: 255 (dcti off) ?001?: 2 ?010?: 3 ?011?: 4 ?100?: 6 ?101?: 8 ?110?: 10 ?111?: 12 d1-d0 ascentcti [bp-dp] gain of dcti function ?00?: 1/4 ?01?: 1/2 ?10?: 1 ?11?: 2 table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 64 aug. 16, 2004; 6251-552-1ds micronas subaddress 31h d7-d4 hcof [bp-dp] peaking: high-pass filter adjustments ?0000?: 0 ?0001?: 1/4 ... ?0100?: 1 ... ?1100?: 12/4 ?1101?: 14/4 ?1110?: 16/4 ?1111?: 20/4 d3-d0 bcof [bp-dp] peaking: band-pass filter adjustments ?0000?: 0 ?0001?: 1/4 ... ?0100?: 1 ... ?1100?: 12/4 ?1101?: 14/4 ?1110?: 16/4 ?1111?: 20/4 subaddress 32h d7-d6 autofrrn [bp-dp] automatic freerun when sync-separartion not stable ?00?: disabled (keep h/v locked, if selected) ?01?: use vertical freerun ?10?: use horizontal freerun ?11?: use horizontal and vertical freerun d5-d4 alpfop9-8 [bp-dp] active lines per field output ?0000000000?: 0 (minimum) ?0100100000?: 288 (default) ?1111111111?: 1023 (maximum) d3 finedel [bp-dp] luminance fine delay output ?0?: no delay ?1?: +1 clkb72 (13.9 ns for tv signal) d2-d0 coarsedel [bp-dp] luminance coarse delay output granularity: 1 clkb36 (27.8 ns for tv signal) ?000?: ? subaddress 33h d7-d0 alpfop7-0 [bp-pm] belongs to 32h subaddress 34h d7-d0 bordposv [bp-pm] borderposition vertical granularity: 2 lines ?00000000?: no border ?11111111?: border at 512 lines at top and bottom table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 65 subaddress 35h d7-d0 bordposh7-0 [bp-pm] borderposition horizontal granularity: 2 pixel ?0000000000?: no border ?1111111111?: border at 2048 pixel on left and right subaddress 36h d7 blanpol [bp-pm] blanking signal polarity ?0?: active high ?1?: active low d6 blanen [bp-pm] blanking signal enable ?0?: disabled (pin 8 can be used as 656vin) ?1?: enabled d5-d4 bordposh 9-8 [bp-pm] belongs to 35h d3-d0 yborder [bp-pm] luminance value for border ?0000?: sub black ?0001?: black ?1111?: white subaddress 37h d7-d4 uborder [bp-pm] chrominance (u) value for border ?1000?: ?0000?: ?no color? u ?0111?: d3-d0 vborder [bp-pm] chrominance (v) value for border ?1000?: ?0000?: ?no color? v ?0111?: subaddress 38h d7-d0 horwidth7-0 [bp-pm] horizontal picture width granularity: 2 pixel ?00000000000?: no display ?00111100000?: 960 pixel ?11111111111?: 4094 pixel note: should be set equal to applop (3dh) table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 66 aug. 16, 2004; 6251-552-1ds micronas subaddress 39h d7-d6 windvsp [bp-pm] vertical windowing: speed ?00?: slow ?01?: medium ?10?: fast ?11?: very fast d5 windvst [bp-pm] vertical windowing: start ?0?: window is closed ?1?: window is open d4 windvdr [bp-pm] vertical windowing: direction ?0?: open the vertical window ?1?: close the vertical window d3 windvon [bp-pm] vertical windowing: enable ?0?: off ?1?: on d2-d0 horwidth 10-8 [bp-pm] belongs to 38h subaddress 3ah d7-d0 horpos7-0 [bp-pm] horizontal position inside active picture area granularity: 2 pixel ?00000000000?: most left display position ?11111111111?: most right display position subaddress 3bh d7-d6 windhsp [bp-pm] horizontal windowing: speed ?00?: slow ?01?: medium ?10?: fast ?11?: very fast d5 windhst [bp-pm] horizontal windowing: start ?0?: window is closed ?1?: window is open d4 windhdr [bp-pm] horizontal windowing: direction ?0?: open the horizontal window ?1?: close the horizontal window d3 windhon [bp-pm] horizontal windowing: enable ?0?: off ?1?: on d2-d0 horpos10-8 [bp-pm] belongs to 3ah table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 67 subaddress 3ch d7 nosync [bp-odc] no horizontal synchronization ?0?: horizontal synchronization ?1?: no horizontal synchronization d6-d4 pploff [bp-odc] synchronization offset (for switching from hor. freerun mode to locked mode) granularity: 4 pixel ?000?: 0 (disabled) ?010?: 8 ?111?: 28 d3-d0 lpfopff [bp-odc] lines per field offset: (for switching from vertical freerun mode to locked mode) granularity: 2 lines ?0000?: 0 (disabled) ?0110?:12 ?1111?: 31 subaddress 3dh d7 chrshft [bp-o/m] chrominance shift shifts the chrominance signal ?0?: no shift ?1?: one line upward d6-d0 applop [bp-o/m] active pixel per line output: granularity: 16 pixel ?0000000?: 0 pixel ?0111100?: 960 pixel ?1111111?: 2032 pixel subaddress 3eh d7-d0 houtdel7-0 [bp-odc] h sync output delay: granularity: 4 pixel ?0000000000?: no delay ?0000000001?: 4 pixel delay ?1111111111?: 4092 pixel delay table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 68 aug. 16, 2004; 6251-552-1ds micronas subaddress 3fh d7-d6 napplop9-8 [bp-o/m] not active pixel per line output: granularity: 4 pixel ?0000000100?: 16 not active pixel ?1111111111?: 4092 not active pixel d5 pdgsr [bp-o/m] switch for vsync transfer algorithm: ?0?: vsync transfer algorithm is enabled ?1?: vsync transfer algorithm is disabled d4 freeze [bp-o/m] freeze picture ?0?: live ?1?: frozen (data writing disabled) d3-d2 stopmode [bp-o/m] operation mode for scan rate conversion: ?00?: aabb (raster | | ||| subaddress 40h d7-d0 napplop7-0 [bp-odc] belongs to 3fh table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 69 subaddress 41h d7-d6 pplop9-8 [bp-o/m] pixel per line output: granularity:4 ?0000000000?: 0 pixel ?0100100000?: 1152 pixel ?1111111111?: 4092 pixel d5 refrper [bp-o/m] refresh period of the memory ?0?: ~5 ms ?1?: ~2,5 ms d4 refron [bp-o/m] refresh on ?0?: no memory refresh ?1?: memory refresh active d3 houtpol [bp-o/m] hout polarity: ?0?: high active ?1?: low active d2 voutpol [bp-o/m] vout polarity: ?0?: high active ?1?: low active d1 houtfr [bp-o/m] hout freerun ?0?: locked mode ?1?: freerun mode d0 voutfr [bp-o/m] vout freerun ?0?: locked mode ?1?: freerun mode subaddress 42h d7-d0 pplop7-0 [bp-o/m] belongs to 41h subaddress 43h d7-d0 lpfop7-0 [bp-odc] lines per field output: only used for freerun mode granularity: 2 lines ?000000000?: no lines ?010011100?: 312 lines ?111111111:? 1022 lines subaddress 44h d7-d0 opdel7-0 [bp-odc] v delay for output operation: ?000000000?: no delay ?010101010?: 170 lines ?111111111?: 511 lines table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 70 aug. 16, 2004; 6251-552-1ds micronas subaddress 45h d7-d6 borderv [bp-o/m] border v ?00?: both borders are displayed ?01?: only lower border is displayed ?10?: only upper border is displayed ?11?: (reserved) d5-d4 borderh [bp-o/m] border h ?00?: both borders are displayed ?01?: only right border is displayed ?10?: only left border is displayed ?11?: (reserved) d3 rdctrldis [bp-o/m] memory read control circuit disable ?0?: enabled ?1?: disabled d2 lpfop8 [bp-o/m] belongs to 43h d1 nalpfop8 [bp-o/m] not active lines output nalpfop-1 lines are not active lines. ?000000001?: all lines active ?000011001?: 24 lines not active ?111111111?: 510 lines not active d0 opdel8 [bp-o/m] belongs to 44h subaddress 46h d7-d0 nalpfop7-0 [bp-odc] belongs to 45h subaddress 47h d6-d5 paldel [cp-cd] pal/ntsc delay vs. secam (chrominance) ?00?: pal/ntsc most left ?11?: pal/ntsc most right d4-d3 locksp [cp-cd] duration of chroma pll search ?00?: 25 fields ?01?: 20 fields ?10?: 17 fields ?11?: 15 fields d2-d0 bgpos [cp-cd] burstgate delay (secam only) granularity: 200 ns ?000?: most left ( ? subaddress 48h d7-d0 hinc0_7-0 [bp-pos] horizontal post-scaler increment 0 ?100000000?: ? table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 71 subaddress 49h d7-d0 hinc1_7-0 [bp-pos] horizontal post-scaler increment 1 ?100000000?: ? subaddress 4ah d7-d0 hinc2_7-0 [bp-pos] horizontal post-scaler increment 2 ?100000000?: ? subaddress 4bh d7-d0 hinc3_7-0 [bp-pos] horizontal post-scaler increment 3 ?100000000?: ? subaddress 4ch d7-d0 hinc4_7-0 [bp-pos] horizontal post-scaler increment 4 ?100000000?: -32 pixel ?000000000?: 0 pixel ?011111111?: 31.875 pixel subaddress 4dh d7 v656del [bp-pos] v656 delay 0: identical delay for modification 1: field 0 is one line shorter note: has only effect when afproc =1 d6 afproc [bp-pos] active field processing for 656v generation 0: inverted active field used as v-sync output 1: v-sync modifies end of active video d5 clkoutsel72 [bp-pos] output clock select 0: clkout depends on clkoutsel 1: clkout is identical to clkb72 d4 hinc4_8 [bp-pos] belongs to 4ch d3 hinc3_8 [bp-pos] belongs to 4bh d2 hinc2_8 [bp-pos] belongs to 4ah d1 hinc1_8 [bp-pos] belongs to 49h d0 hinc0_8 [bp-pos] belongs to 48h table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 72 aug. 16, 2004; 6251-552-1ds micronas subaddress 4eh d7-d0 hscposc7-0 [bp-pos] horizontal scaling factor for post scaler ?010000000000?: factor is 4 ?101101010101?: factor is 1.407 (682 subaddress 4fh d7 cdelhpos [bp-pos] chrominance delay 0: no delay 1: half-pixel delay d6 clkoutsel [bp-pos] output clock select 0: clkout is identical to clkb27 1: clkout is identical to clkb36 note: hsync, vsync, blank are transferred to selected clock d5 clkoutinv [bp-pos] clkout inversion 0: no inverted clkout 1: inverted clkout d4 hpanon [bp-pos] panorama mode enable ?0?: panorama mode disabled ?1?: panorama mode enabled d3-d0 hscposc 11-8 [bp-pos] belongs to 4eh subaddress 50h d7-d0 hseg1_7-0 [bp-pos] beginning of segment 1 for panorama mode granularity: 2 pixel ?00000000000?: 0 pixel behind picture start ?11111111111?: 4094 pixel behind picture start subaddress 51h d7-d0 hseg2_7-0 [bp-pos] beginning of segment 2 for panorama mode granularity: 2 pixel ?00000000000?: 0 pixel behind picture start ?11111111111?: 4094 pixel behind picture start subaddress 52h d7-d0 hseg3_7-0 [bp-pos] beginning of segment 3 for panorama mode granularity: 2 pixel ?00000000000?: 0 pixel behind picture start ?11111111111?: 4094 pixel behind picture start subaddress 53h d7-d0 hseg4_7-0 [bp-pos] beginning of segment 4 for panorama mode granularity: 2 pixel ?00000000000?: 0 pixel behind picture start ?11111111111?: 4094 pixel behind picture start table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 73 subaddress 54h d7 fioffoff [bp-pos] fieldoffset for itu656 ntsc signals ?0?: disabled ?1?: enabled d6 fieldbinv [bp-pos] backend field inversion ?0?: no inversion ?1?: inversion d5-d3 hseg2_10-8 [bp-pos] belongs to 51h d2-d0 hseg1_10-8 [bp-pos] belongs to 50h subaddress 55h d7 chrmsig656 [bp-pos] chrominance format for 656 output ?0?: (r ? ? ? ? ? ? vertical pulse delay backend (test only) ?0?: no delay ?1?: delayed d5-d3 hseg4_10-8 [bp-pos] belongs to 53h d2-d0 hseg3_10-8 [bp-pos] belongs to 52h subaddress 56h d7 shiftuv [bp-dac] shift uv subsampling at digital output ?0?: take first uv couple ?1?: take second uv couple vsp9432/42 only d6 dpout656 [bp-dac] enable digital 656 output ?0?: disable output ?1?: enable output subaddress 57h d7 chromsign [bp-dac] chrominance sign ?0?: (r ? ? ? ? ? ? chrominance amplification ?0?: amplification=1 ?1?: amplification=2 subaddress 58h d7-d0 pkly [bp-dac] voltage level for y dac output ?00000000?: 0.4 v ?10000000?: 1.0 v ?11111111?: 1.9 v including peaking overshoots. 0.9 v for white max. table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 74 aug. 16, 2004; 6251-552-1ds micronas subaddress 59h d7-d0 pklu [bp-dac] voltage level for u dac output ?00000000?: 0.4 v ?10000000?: 1.0 v ?11111111?: 1.9 v subaddress 5ah d7-d0 pklv [bp-dac] voltage level for v dac output ?00000000?: 0.4 v ?10000000?: 1.0 v ?11111111?: 1.9 v subaddress 5bh d7-d5 cons [cp-cd] color switched on (secam) at level=ckills+cons ?000?: min value ?010?: default ?111?: max value d4 colon [cp-cd] force color on ?0?: color depends on color decoder status ?1?: color always on d3-d2 crcb [cp-cd] choice of uv or crcb output 00: uv color space 01: crcb color space 10: modified crcb color space (secam only; pal & ntsc: same as setting ?01?) d1 accfix [cp-cd] fix acc to nominal value ?0?: acc is working ?1?: acc is fixed d0 accfrz [cp-cd] freeze acc ?0?: acc is working ?1?: acc is frozen table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 75 subaddress 5ch d7-d5 con [cp-cd] color switched on (pal/ntsc) at level=ckill+con ?000?: min value ?010?: default ?111?: max value d4-d3 uvcor [cp-cd] chrominance coring ?00?: off ?01?: luminance notch-filter ?0?: notch-filter enabled ?1?: notch-filter bypassed d1-d0 secntch [cp-cd] selection of notch filter behavior in secam mode ?00?: 4.406 mhz ?01?: 4.250 mhz ?10?: 4.33 mhz ?11?: 4.406 / 4.25 dependent on transmitted color subaddress 5dh d7-d6 pwthd [cp-cd] selection of ? peak-white? threshold ?00?: 448 ?01?: 470 ?10?: 500 ?11?: 511 d5-d4 clrange [cp-cd] chroma lock-range ?00?: luminance offset in color decoder during visible picture ?00?: no offset ?01?: ? ? ? ? note: a 7.5 ire offset is added during blanking in display processing. when choosing ? 10?, the luminance offset is equal to the offset of the cvbs input as in both picture and blanking the same 7.5 ire offset is used. d1 vdetifs [cp-cd] vertical sync-detection slope ?0?: normal ?1?: slow table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 76 aug. 16, 2004; 6251-552-1ds micronas subaddress 5eh d7-d6 sdr [cp-cd] secam dr adjustment 00: 191 01: 194 10: 197 11: 200 d5-d0 chrf [cp-cd] chroma bandwidth selects chroma bandwidth ?011100?: nominal bandwidth subaddress 5fh d7 comb [cp-cd] delay line ?0?: use delay line ?1?: do not use delay line (only suited for ntsc) d6-d0 cstand [cp-cd] color standard assignment ?0000000?: no color standard chosen ?0000001?: pal n ?0000010?: pal b ?0000100?: secam ?0001000?: pal 60 ?0010000?: pal m ?0100000?: ntsc m ?1000000?: ntsc 44 for allowed combinations please refer to chapter (see section 2.1.5. on page 9) ?1100110?: palb/secam/ntscm/ntsc44/pal60 subaddress 60h d7-d0 ckill [cp-cd] chroma level for color off (pal/ntsc) ?00000000?: high burst amplitude ?01000000?: default ?11111111?: low burst amplitude subaddress 61h d7-d0 ckills [cp-cd] chroma level for color off (secam) ?00000000?: low burst amplitude ?01000000?: default ?11111111?: high burst amplitude table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 77 subaddress 62h d7-d6 vpol [cp-cd] v polarity at vinp ?00?: use vsync ?01?: use inverted vsync ?10?: autodetect polarity ?11?: (reserved) d5 lppost [cp-cd] additional filtering of luminance ?0?: no filtering ?1?: filtering d4-d0 ycdel [cp-cd] luminance delay ?10000?: 800 ns ?0000?: no delay ?01111?: ? subaddress 63h d7-d0 hue [cp-cd] hue control (tint) ?10000000?: ? subaddress 64h d7-d0 ntscref [cp-cd] acc reference adjustment (ntsc) ?00000000?: low reference value ?10100101?: nominal value ?11111111?: high reference value subaddress 65h d7-d0 palref [cp-cd] acc reference adjustment (pal) ?00000000?: low reference value ?01011111?: nominal value ?11111111?: high reference value subaddress 66h d7-d6 sllthd [cp-cd] slicing level threshold h ?00?: no offset ?01?: small negative ?10?: small positive ?11?: large positive (adaptive) d5-d0 scadj [cp-cd] subcarrier adjustment ?000000?: ? table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 78 aug. 16, 2004; 6251-552-1ds micronas subaddress 67h d7-d6 agcmd [cp-cd] agc method ?00?: sync amplitude and peak white ?01?: sync amplitude only ?10?: peak white only ?11?: fixed to value agcadj1 d5-d0 agcadj1 [cp-cd] automatic gain adjustment adc1 ?000000?: 0.6 v input signal ?111111?: 1.8 v input signal subaddress 68h d7 agcres [cp-cd] agc reset ?0?: no reset ?1?: reset d6 agcfrze [cp-cd] freeze agc (adc_cvbs) ?0?: normal operation ?1?: freeze agc at current value d5-d0 agcadj2 [cp-cd] automatic gain adjustment adc2 ?000000?: 0.6 v input signal ?111111?: 1.8 v input signal subaddress 69h d7-d0 clmphigh [cp-cd] vertical end of clamping pulse granularity: 2 ?00000000?: line 256 ?00111100?: line 376 ?11111111?: line 766 subaddress 6ah d7-d4 cvbosel1 [cp-cd] output select 1 for pin cvbso1 ?0000?: cvbs1 ?0001?: cvbs2 ?0010?: cvbs3 ?0011?: cvbs4 or y1 ?0100?: cvbs5 or c1 ?0101?: cvbs6 or y2 ?0110?: cvbs7 or c2 ?0111?: y1 + c1 ?1000?: y2 + c2 d3-d0 clmplow [cp-cd] vertical start of clamping pulse ?0000?: line 0 ?0011?: line 6 ?1111?: line30 table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 79 subaddress 6bh d7 fline [cp-cd] mode selection ?0?: interlace input ?1?: progressive input d6 fldinv [cp-cd] field inversion ?0?: no inversion ?1?: inversion d5 clpstgy [cp-cd] clamping strategy ?0?: back-porch clamping ?1?: sync-tip-clamping d4 ycsel [cp-cd] y/c select ?0?: cvbs input ?1?: y/c input d3-d0 clmpd1 [cp-cd] measurement duration adc1 granularity: 200 ns ?0000?: 0 subaddress 6ch d7-d6 hpol [cp-cd] h polarity at hinp ?00?: use hsync ?01?: use inverted hsync ?10?: autodetect polarity ?11?: (reserved) d5 fhdet [cp-cd] automatic multisync capability ?0?: disabled ?1?: enabled d4 dischch [cp-cd] channel-change signal for color decoder ?0?: color-decoder not reset after channel-change ?1?: color-decoder reset after channel-change d3-d0 clmpd2 [cp-cd] measurement duration adc2 granularity: 200 ns ?0000?: 0 table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 80 aug. 16, 2004; 6251-552-1ds micronas subaddress 6dh d7 nosigb [cp-cd] no signal behavior ?0?: noisy screen when out of sync ?1?: colored background insertion instead d6 hinp [cp-cd] horizontal pulse detection ?0?: from cvbs adc1 ?1?: from rgbf adc d5-d0 clmpst1 [cp-cd] measurement start adc1 ?000000?: 0 subaddress 6eh d7-d6 plltc [cp-cd] time constant hpll (vcr...tv) ?00?: very fast ?01?: fast ?10?: slow ?11?: very slow d5-d0 clmpst2 [cp-cd] measurement start adc2 ?000000?: 0 subaddress 6fh d7-d4 cvbsel2 [cp-cd] input select for adc2 ?0000?: cvbs1 ?0001?: cvbs2 ?0010?: cvbs3 ?0011?: cvbs4 or y1 ?0100?: cvbs5 or c1 ?0101?: cvbs6 or y2 ?0110?: cvbs7 or c2 ?0111?: y1 + c1 ?1000?: y2 + c2 ?1111?: disabled d3-d0 cvbsel1 [cp-cd] input select for adc1 ?0000?: cvbs1 ?0001?: cvbs2 ?0010?: cvbs3 ?0011?: cvbs4 or y1 ?0100?: cvbs5 or c1 ?0101?: cvbs6 or y2 ?0110?: cvbs7 or c2 ?0111?: y1 + c1 ?1000?: y2 + c2 ?1111?: disabled table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 81 subaddress 70h d7-d4 cvbosel2 [cp-cd] output select for pin cvbso2 ?0000?: cvbs1 ?0001?: cvbs2 ?0010?: cvbs3 ?0011?: cvbs4 or y1 ?0100?: cvbs5 or c1 ?0101?: cvbs6 or y2 ?0110?: cvbs7 or c2 ?0111?: y1 + c1 ?1000?: y2 + c2 d3-d0 cvbosel3 [cp-cd] output select for pin cvbso3 ?0000?: cvbs1 ?0001?: cvbs2 ?0010?: cvbs3 ?0011?: cvbs4 or y1 ?0100?: cvbs5 or c1 ?0101?: cvbs6 or y2 ?0110?: cvbs7 or c2 ?0111?: y1 + c1 ?1000?: y2 + c2 subaddress 71h d7-d0 fhfrrn [cp-cd] free running frequency of horizontal pll ?00000000?: 384 clocks (52.7 khz) ?11100100?: 1296 clocks (15.625 khz) ?11111111?: 1404 clocks (14.423 khz) table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 82 aug. 16, 2004; 6251-552-1ds micronas subaddress 72h d7 reftrimen [cp-cd] reference value enable ?0?: use fuses ?1?: uses programmed value d6 satnr [cp-cd] noise reduction for satellite signal ?0?: disabled ?1?: enabled d5 vinp [cp-cd] vertical pulse detection ?0?: from cvbs signal ?1?: from v-input pin d4-d3 nsred1-0 [cp-cd] noise reduction for horizontal pll ?000?: 1/16 ?001?: 1/8 ?010?: 1/4 ?011?: 1/2 ?100?: 1 ?101?: 2 ?110?: 4 ?111?: 8 msb is at address 7eh, d2 d2-d0 lpcdel [cp-cd] window shift for fine error calculation ?100?: ? subaddress 73h d7-d0 vshift [cp-cd] field detection window shift ?00000000?: no shift ?11111111?: shifted by 2048 subaddress 74h d7 palidl1 [cp-cd] pal/ntsc identification level 1 ?0?: less sensitive (192) ?1?: more sensitive (64) d6-d0 vthrl50 [cp-cd] vertical window noise suppression opening opening= 4* vthrl50 0000000: opening in first line 1111111: opening in line 508 subaddress 75h d7 palidl0 [cp-cd] pal/ntsc identification level 0 ?0?: less sensitive ?1?: more sensitive d6-d0 vthrh50 [cp-cd] vertical window noise suppression closing closing= 312+4* vthrh50 0000000: closing in line 312 1111111: closing in line 820 when vinp (72h) is set, 50 hz values are taken for opening and closing val- ues. table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 83 subaddress 76h d7-d0 reftrim [cp-cd] reference value bandgap ?01000000?: low reference ?00000000?: medium reference ?01111111?: high reference ?1xxxxxxx?: reference disa bled, resistor used subaddress 77h d7-d4 reftrimcv [cp-cd] reference value adc cvbs (antialiasfilter) ?0000?: narrow ?1111?: wide d3-d0 reftrimrgb [cp-cd] reference value adc rgbf (antialiasfilter) ?0000?: narrow ?1111?: wide subaddress 78h d7 sllthdvp [cp-cd] vertical slicing level threshold polarity ?0?: positive ?1?: negative d6 thrsel [cp-cd] h slicing level threshold ?0?: 50 % ?1?: 37 % d5-d0 clmpst1s [cp-cd] clamping start for adc1 ?000000?: 0 subaddress 79h d7-d6 scmidl [cp-cd] secam identification level ?00?: 128 ?01?: 64 ?10?: 96 ?11?: 80 d5-d0 clmpst2s [cp-cd] clamping start adc2 ?000000?: 0 table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 84 aug. 16, 2004; 6251-552-1ds micronas subaddress 7ah d7-d3 acclim [cp-cd] acc-limitation for weak signals ?00000?: strong limitation ?11111?: no limitation d2-d0 ifcomp [cp-cd] if compensation filter ?000?: pal prefiltering ?001?: pal prefiltering + if ?010?: prefiltering ?011?: if 6db ?100?: flat note: ? 000? or ? 001? are not suited for 3.58 mhz subcarrier color standards (pal m, pal n, ntsc m) subaddress 7bh d7-d4 clmpd2s [cp-cd] clamping duration for adc2 granularity: 200 ns ?0000?: 0 clamping duration for adc1 granularity: 200 ns ?0000?: 0 subaddress 7ch d5 eia770 [cp-cd] eia 770 support ?0?: standard tv signals expected ?1?: progressive signals expected timing according to eia 770.1 or eia 770.2 when ?1? d4 shaperdis [cp-pp] power down of crystal oscillator shaper ?0?: normal operation ?1?: power down active d3 oscpd [cp-pp] power down of crystal oscillator amplifier ?0?: normal mode ?1?: power down mode d2 tstshaperi [cp-pp] testmode control of crystal oscillator ?0?: normal operation (shaper active) ?1?: external clock input (shaper replaced) d1-d0 freqsel [cp-pp] amplifier current setting of oscillator pad ?00?: 100 table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 85 subaddress 7dh d6-d4 bellfir [cp-cd] bell filter fir component ?000?: ? ? ? ? ? ? ? ? bell filter iir component ?000?: 8 ?001?: 9 ?010?: 10 ?011?: 11 ?100?: 12 ?101?: 13 ?110?: 14 ?111?: 16 d0 vflywhl [cp-cd] vertical flywheel ?0?: disabled ?1?: enabled subaddress 7eh d7-d6 flnstrd [cp-cd] force line standard at cvbs/rgb frontend ?00?: automatic ?01?: force 50 hz ?10?: force 60 hz ?11?: (reserved) d5 enlim [cp-cd] enable limiter ?0?: disabled ?1?: enabled d4-d3 ishft [cp-cd] i-adjustment for horizontal pll ?00?: *1 ?01?: *2 ?10?: *4 ?11?: *8 d2 nsred2 [cp-cd] belongs to 72h d1-d0 vlp [cp-cd] lowpass for vertical sync-separation ?00?: none ?01?: weak ?10?: medium ?11?: strong table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 86 aug. 16, 2004; 6251-552-1ds micronas subaddress 7fh d7 secacc [cp-cd] secam acceptance ?0?: disabled ?1?: enabled d6 secdiv [cp-cd] secam divider ?0?: divide by 4 ?1?: divide by 2 d5-d4 secinc1 [cp-cd] secam increment 1 ?00?: 2 ?01?: 3 ?10?: 4 ?11?: 5 d3-d2 secinc2 [cp-cd] secam increment 2 ?00?: 1 ?01?: 2 ?10?: 3 ?11?: 4 d1-d0 scmrel [cp-cd] secam rejection level ?00?: 320 ?01?: 384 ?10?: 352 ?11?: 1024 table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 87 subaddress 80h d7 porcncl [cp-cd] reset control bit cancel ?0?: no operation ?1?: reset por bit (8ch) after use, porcncl must be set to ?0? again d6-d4 ntchsel [cp-cd] luminance notch selection ?000?: sharp notch ?001?: medium 1 ?010?: medium 2 ?011?: broad notch ?100?: broad steep notch (pal, secam only) d3 cpllres [cp-cd] force chroma pll reset ?0?: no reset ?1?: reset chroma pll after use, cpllres must be set to ?0? again d2 disallres [cp-cd] disable all chroma resets ?0?: resets allowed ?1?: resets disabled may only be used if one color standard is selected d1 trapblu [cp-cd] notchfrequency for 4,250 mhz ?0?: 4.25 mhz ?1?: 4.2 mhz has only effect in secam mode d0 trapred [cp-cd] notchfrequency for 4,406 mhz ?0?: 4.406 mhz ?1?: 4.356 mhz has only effect in secam mode table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 88 aug. 16, 2004; 6251-552-1ds micronas subaddress 80h d7 porcncl [cp-cd] reset control bit cancel ?0?: no operation ?1?: reset por bit (8ch) after use, porcncl must be set to ?0? again d6-d4 ntchsel [cp-cd] luminance notch selection ?000?: sharp notch ?001?: medium 1 ?010?: medium 2 ?011?: broad notch ?100?: broad steep notch (pal, secam only) d3 cpllres [cp-cd] force chroma pll reset ?0?: no reset ?1?: reset chroma pll after use, cpllres must be set to ?0? again d2 disallres [cp-cd] disable all chroma resets ?0?: resets allowed ?1?: resets disabled may only be used if one color standard is selected d1 trapblu [cp-cd] notchfrequency for 4,250 mhz ?0?: 4.25 mhz ?1?: 4.2 mhz note: has only effect in secam mode d0 trapred [cp-cd] notchfrequency for 4,406 mhz ?0?: 4.06 mhz ?1?: 4.356 mhz note: has only effect in secam mode table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 89 subaddress 81h d7 adlck [cp-cd] additional lock-detection ?0?: no used ?1?: used d6 adlcksel [cp-cd] additional lock-detection selection ?0?: palid ?1?: paldet d5 adlckcc [cp-cd] additional lock-detection color-killer ?0?: do not use lock signal ?1?: use lock-signal d4-d3 vflywhlmd[cp- cd] vertical flywheel mode ?00?: check for correct standard ?01?: 3 lines deviation allowed ?10?: 4 lines deviation allowed, no check for interlace ?11?: 5 lines deviation allowed, no check for interlace d2-d0 secaccl [cp-cd] secam acceptance level ?000?: 100 ?001?: 84 ?010?: 64 ?011?: 32 ?100?: 70 ?101?: 76 ?110?: 90 note: must be enabled by secacc (7fh) to have an effect table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 90 aug. 16, 2004; 6251-552-1ds micronas subaddress 82h (no auto-increment) d7-d6 syncfthd [cp-cd] syncf threshold 00: 4 lines 01: 3 lines 10: 2 lines 11: 1 line d5 ifcompstr [cp-cd] 2nd if compensation filter ?0?: disabled ?1?: enabled d4 palidl2 [cp-cd] pal/ntsc identifikation level 2 ?0?: less sensitive ?1?: more sensitive d3 cpllof [cp-cd] chroma pll open ?0?: normal operation ?1?: chroma pll opened d2 deempstd [cp-cd] deemphase filtering for standard detection ?0?: weak ?1?: strong d1 palinc1 [cp-cd] pal/ntsc detection: increment 1 ?0?: +3 ?1?: +2 d0 palinc2 [cp-cd] pal/ntsc detection: increment 2 ?0?: ? ? subaddress 83h (read-only) d0 fblactive [cp-i2c] activity at fbl input ?0?: no activity ?1?: activity reset automatically when read subaddress 84h (read-only, no auto-increment)) d6-d0 noiseme [fp-tnr] noise level of the input signal 0000000: no noise 1111110: strong noise 1111111: strong noise or measurement failed note: no autoincrement possible table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 91 subaddress 85h (read-only) d5 lbstatus [fp-tnr] status bit for letter box detection: 0: no new value available 1: new value from letter box detection available note: reset automatically when read d4 pfbl [fp-tnr] indicates overflow at fbl input ?0?: no overflow ?1?: overflow note: reset automatically when read d3 pg [fp-tnr] indicates overflow at green input ?0?: no overflow ?1?: overflow note: reset automatically when read d2 pb [fp-tnr] indicates overflow at blue input ?0?: no overflow ?1?: overflow note: reset automatically when read d1 pr [fp-tnr] indicates overflow at red input ?0?: no overflow ?1?: overflow note: reset automatically when read d0 nmstatus [fp-tnr] indicates new value of the noise measurement 0: noiseme has not been updated 1: new value of noiseme available note: reset automatically when read subaddress 86h (read-only) d0 stabll [pp] shows ll-hpll lock status ?0?: ll_hpll is not locked ?1?: ll_hpll is locked subaddress 87h (read-only) d1-d0 smmirror [bp-o/m] operation mode for scan rate conversion: ?00?: aabb (raster | | ||| table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 92 aug. 16, 2004; 6251-552-1ds micronas subaddress 88h (read-only) d7 dethpol [cp-cd] detected polarity of hsync ?0?: negative ?1?: positive d6 detvpol [cp-cd] detected polarity of v sync ?0?: negative ?1?: positive d5-d3 stdet [cp-cd] detected color standard ?000?: non standard or standard not detected ?001?: ntsc m ?010?: pal m ?011?: ntsc44 ?100?: pal60 ?101?: pal n ?110?: secam ?111?: pal b/g d2 scouten [cp-cd] scdev valid indication ?0?: scdev not valid ?1?: scdev valid d1 palid [cp-cd] pal identification (algorithm 1) ?0?: not pal ?1?: pal d0 ckstat [cp-cd] colorkill status ?0?: color off ?1?: color on subaddress 89h (read-only) d7 lnstdrd [cp-cd] line standard detection ?0?: 60 hz ?1?: 50 hz d6 int [cp-cd] interlace detection ?0?: progressive input ?1?: interlace input d5-d0 scdev [cp-cd] deviation of clock system or color carrier ?100000?: max. negative deviation ?000000?: no deviation ?011111?: max. positive deviation subaddress 8ah (read-only) d7-d0 lpfld [cp-cd] nr. of lines per field for input signal lines= 256+ lpfld *2 ?00000000?: 256 lines or less ?11111111?: 766 lines or more table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 93 subaddress 8bh (read-only) d7-d0 nrpixel [cp-cd] pixel number of input signal granularity: 4 ?00000000?: 384 or less ?11111111?: 1404 or more pixel=4* nrpixel +384 subaddress 8ch (read-only) d7 por [cp-cd] reset indication a reset at pin 24 (reset) sets por . por is reset with porcncl (80h) ?0?: no reset appeared ?1?: reset appeared d3 vflymd [cp-cd] vertical flywheel mode locked 0: unlocked 1: locked vflywhl must be enabled to give a result d2 stab [cp-cd] status of horizontal synchronization ?0?: sync separation not locked ?1?: sync separation locked and stable d0 paldet [cp-cd] pal identification (algorithm 2) ?0?: not pal ?1?: pal subaddress 8dh (read-only) d7-d0 reftrimrd [cp-cd] reference value bandgap ?01000000?: low reference ?00000000?: medium reference ?01111111?: high reference ?1xxxxxxx?: reference disa bled, resistor used note: contains fused value only when reftrimen (72h)=0. subaddress 8eh (read-only) d7-d4 reftrimcvrd [cp-cd] reference value cvbs adc ?0000?: narrow ?1111?: wide note: contains fused value only when reftrimen (72h)=0. d3-d0 reftrimrgbrd [cp-cd] reference value rgb adc ?0000?: narrow ?1111?: wide note: contains fused value only when reftrimen (72h)=0. table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 94 aug. 16, 2004; 6251-552-1ds micronas subaddress 8fh (read-only, not compatible to 940x family) d3 sls [cp-i2c] line standard at device output ?0?: 100 hz (vsp 9402a, vsp 9412a) ?1?: 50 hz (vsp 9432a, vsp 9442a) d2-d0 version [cp-i2c] version of vsp 94xx family ?001?: vsp 94x5b ?010?: vsp 94x2a ?011?: vsp 94x7b ?101?: vsp 94x9c others: reserved subaddress 90h (read-only) d7 am50o [cp-i2c] last detected standard 50 hz ?0?: pal or none ?1?: secam d6 am60o [cp-i2c] last detected standard 60 hz ?0?: ntsc m or none ?1?: ntsc44 or pal60 d5-d0 agcadjcv [cp-i2c] agc value for adc1 000000: smallest input range 111111: biggest input range subaddress 91h (read-only) d6-d0 vlength [cp-i2c] length of vertical pulse 0000000: short v 1111111: long v subaddress 92h (read-only) d7-d0 minv [cp-i2c] measured sync amplitude 00000000: smallest sync 11111111: largest sync subaddress 93h (read-only) d4-d0 pwadjcnt [cp-i2c] peak white adjust counter 00000: no pw reduction 11111: largest pw reduction subaddress 96h (read-only) d0 v40stat [fp-i2c] v status bit of 40.5 mhz domain ?0?: new write or read cycle can start ?1?: no new write or read cycle can start subaddress 98h (read-only) d0 v36bstat [bp-i2c] v status bit of backend 36 mhz domain ?0?: new write or read cycle can start ?1?: no new write or read cycle can start table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 95 subaddress 99h (read-only) d0 v20stat [cp-i2c] v status bit of 20.25 mhz domain ?0?: new write or read cycle can start ?1?: no new write or read cycle can start subaddress a0h d7-d4 kpnl [pp] proportional factor for loop filter if hpll is not locked same values as in locked condition (kpl) d3-d0 kpl [pp] proportional factor for loop filter if hpll is locked ) 00000 : 0 00001: 1 00010: 2 00011: 4 00100: 8 00101: 16 00110: 32 00111: 64 01000: 128 01001: 256 01010: 512 01011: 1024 01100: 2048 01101: 4096 01110: 8192 01111:16384 10000: 0.5 10001: 1.5 10010: 2.5 10011: 3 10100: 3.5 10101: 4.5 10110: 5 10111: 6 11000: 7 table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 96 aug. 16, 2004; 6251-552-1ds micronas subaddress a1h d7-d4 kinl [pp] integrational factor for loop filter if hpll is not locked same values as in locked condition (kil) d3-d0 kil [pp] integrational factor for loop filter if hpll is locked 00000 : 0 00001: 1 00010: 2 00011: 4 00100: 8 00101: 16 00110: 32 00111: 64 01000: 128 01001: 256 01010: 512 01011: 1024 01100: 2048 01101: 4096 01110: 8192 01111:16384 10000: 0.5 10001: 1.5 10010: 2.5 10011: 3 10100: 3.5 10101: 4.5 10110: 5 10111: 6 11000: 7 subaddress a2h d7-d0 limip [pp] limiter control for p-part for increased dynamic range limit_p= limip ?00000000?: subaddress a3h d7-d0 limii [pp] limiter control for i-part for increased dynamic range limit_i= limii ?00000000?: table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 97 subaddress a4h d7 kpnl4 [pp] refer to a0h d6 kpl4 [pp] refer to a0h d5 kinl4 [pp] refer to a1h d4 kil4 [pp] refer to a1h d3-d0 limlr [pp] limit ll-pll lock-in range 0000: full lock-in range of subaddress b0 d6-d5 agcthd [cp-cd] agc hysterisys 00: broad 01: medium 1 10: medium 2 11: small d4-d0 femag [cp-cd] fine error characteristic 00000: smallest gain 10000: default (equal to a32 version) 11111: largest gain table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 98 aug. 16, 2004; 6251-552-1ds micronas subaddress b1 d6-d4 sllthdv [cp-cd] slicing level threshold v ?000?: no offset ?001?: 4 ?010?: 8 ?011?:12 ?101?: adaptive (limited to sllthdvp (78h) d3-d2 amstd60 [cp-cd] automatic standard detection priority 60 hz 00: ntsc m 01: ntsc44/pal60 10: (reserved) 11: automatic d1-d0 amstd50 [cp-cd] automatic standard detection priority 50 hz 00: pal b 01: secam 10: (reserved) 11: automatic subaddress b2 d7-d6 sdb [cp-cd] secam db adjustment 00: ? ? ? ? vertical pulse gating 0: disabled 1: enabled d3 mvp [cp-cd] vertical length measurement with vertical pulse detection 0: disabled 1: enabled d2-d0 vdetitc [cp-cd] vertical detection integration time constant 000: 400 clock cycles 001: 375 clock cycles 010: 350 clock cycles 011: 300 clock cycles 100: 250 clock cycles 101: 225 clock cycles 110: 200 clock cycles 111: automatic subaddress b3 d6-d0 vthrl60 [cp-cd] vertical window noise suppression opening opening=4* vthrl60m 0000000: opening in first line 1111111: opening in line 508 table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 99 subaddress b4 d6-d0 vthrh60 [cp-cd] vertical window noise suppression closing closing=262+4* vthrh60m 0000000: closing in line 262 1111111: closing in line 770 subaddress b5 d7-d5 deempiir [cp-cd] deemphase filter iir component ?000?: 5 ?001?: 6 ?010?: 7 ?011?: 8 ?100?: 9 ?101?: 10 ?110?: (reserved) ?111?: (reserved) d3-d0 deempfir [cp-cd] deemphase filter fir component ?0000?: 16 ?0101?: 21 ?1111?: 31 subaddress b7 d7-d0 napplipi [fp-rgb] not active pixels from hsync to input data for itu delay= napplipi * 2 + napipphi subaddress b8 d7-d0 alpfipi [fp-rgb] active lines per field for itu active lines=alpfipi * 2 (int) 144: 288 active lines subaddress b9 d7-d0 applipi [fp-rgb] active pixels per line for itu active pixels= applipi * 2 (int) 360=720 lines subaddress ba d7 applipi[8] [fp-rgb] active pixels per line for itu active pixels= applipi * 2 (int) 360=720 lines d6 nalpfipi [fp-rgb] not active lines per field for itu (int) 20= 20 lines subaddress bch d7-d0 frinc18-11 [pp] set hdto freerunning frequency granularity=103 hz 33981 d (minimum: nominal pixel clock= 3.5 mhz) 349525 d (nominal pixel clock= 36 mhz) 388362 d (maximum: nominal pixel clock= 40 mhz) table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 100 aug. 16, 2004; 6251-552-1ds micronas subaddress bd d7-d0 frinc10-3 [pp] belongs to bch subaddress be d2-d0 frinc2-0 [pp] belongs to bch subaddress c0 d7-d0 hsppl [fp-rgb] hsync shift shift=hsppl * 4 00000000: default subaddress c1 d7 fofst [fp-rgb] offset of active field at interlaced mode (line offset): 0: nalpfipi+1 at field a, nalpfipi at field b 1: nalpfipi at field a, nalpfipi+1 at field b d2-d0 vslpf [fp-rgb] vsync shift shift=vslpf * 4 0000000: default subaddress d0 d7-d6 vblandel [bp-pm] refer to d1h d5 vblanpol [bp-pm] vertikal blank signal polarity 0: positive 1: negative d2 fswftl [bp-pm] stability signal of ll_hpll ?0?: stabll is generated accoding to setstabll ?1?: stabll is forced to 1 (hout synchronization enabled) d1-d0 vblanlen [bp-pm] refer to d2h subaddress d1 d7-d0 vblandel[7:0] [bp-pm] vertical delay in lines from vsync to active edge of blank signal: blank_start=1* vblandel ?0000000000?: no delay ?1111111111?: 1023 lines delay subaddress d2 d7-d0 vblanlen [bp-pm] vertical length in lines from start of active blank signal: blank_length=4* vblanlen ?00000000?: no line ?11111111?: 1020 lines subaddress e0 d7-d0 lbgraddet [fp-rgb] threshold for gradient detected (int) 50: default table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 101 subaddress e1 d7-d0 lbvwendlo [fp-rgb] vertical measure window lower end (int) 150: default, [in lines (*2) related to vsync] subaddress e2 d7-d0 lbhwend [fp-rgb] horizontal measure window end (int) 180: default, [in active pixels (*4) related to hsync] subaddress e3 d7-d0 lbhiwhite [fp-rgb] histogram white (int) 50: default subaddress e4 d7-d0 lbhistbla [fp-rgb] histogram black (int) 25: default subaddress e5 d7 lbmasla [fp-rgb] set to 1 d6-d0 lbvwstlo [fp-rgb] vertical measure window lower start (int) 96: default] , [in lines (*2) related to vsync] subaddress e6 d7 lbfs [fp-rgb] field subsampling mode 0: a+b fields 1: only a field d6-d0 lbvwendup [fp-rgb] vertical measure window upper end (int) 73: default] , [in lines (*2) related to vsync] subaddress e7 d7 lbvisuon [fp-rgb] visualisation of letter box results 0: disabled 1: enabled d6-d0 lbhwst [fp-rgb] horizontal measure window start (int) 36: default, [in active pixels (*4) related to hsync] subaddress e8 d5-d0 lbvwstup [fp-rgb] vertical measure window upper start (int) 20: default ], [in lines (*2) related to vsync] table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 102 aug. 16, 2004; 6251-552-1ds micronas subaddress e9 d7 lbstability [fp-rgb] stability flag 0: continuous format update 1: format update only once d6 lb43sens [fp-rgb] sensitivity to 4:3 switch 0: off 1: on d5 lbngfen [fp-rgb] no gradient found 0: disabled 1: enabled d4-d0 lbthdnbng [fp-rgb] threshold for darkness-brightness, gradient only (int) 15: default ] subaddress ea d7-d6 lbsub [fp-rgb] subsampling mode 0x: 13.5 mhz (1, e.g. digital 656 input) 10: 20.25 mhz source ( 1 .5 , for cvbs, yuv and rgb) 11: 40.5 mhz source (3) d5 lbgradrst [fp-rgb] reset of gradient method 0 : no reset 1: reset d4-d0 lbhsdel [fp-rgb] histogram stability delay ( int)10=default subaddress eb d4-d0 lbthdnbnha [fp-rgb] threshold for darkness-brightness, histogram, activity (int)30=default subaddress ec d4-d0 lbactivity [fp-rgb] activity (int) 5: default ] subaddress ed d4-d0 lbgfbdel [fp-rgb] gradient fall back delay value (int) 11: default ] subaddress ee d4-d0 lbgsdel [fp-rgb] gradient stability delay value (int) 10: default ] subaddress ef d4-d0 lbasdel [fp-rgb] activity stability delay (int) 10: default ] table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 103 subaddress f0 (read only) d7 lbelaa [fp-rgb] refer to f1h d6-d0 lbslaa [fp-rgb] letter box detection: start line of active area lbslaa is measured in relation to vsync subaddress f1 (read only) d7-d0 lbelaa [fp-rgb] letter box detection: end line of active area lbelaa is measured in relation to vsync subaddress f2 (read only) d7 lbformat [fp-rgb] letter box detection: format 0: 4:3 format 1: other format (letter box) d6 lbsubtitle [fp-rgb] letter box detection: subtitle flag 0: no subtitle 1: subtitle available d5 lbtoptitle [fp-rgb] letter box detection: toptitle flag 0: no toptitle 1: toptitle available d4 gradisstable [fp-rgb] letter box detection: gradient is stable internal value, only for test purposes d3 toptitle [fp-rgb] lbd: upper area contains high activity internal value, only for test purposes d2 subtitle [fp-rgb] lbd: lower area contains high activity internal value, only for test purposes d1 nogradfound [fp-rgb] lbd: no gradient found internal value, only for test purposes d0 switchto43 [fp-rgb] lbd: switch to 4:3 format internal value, only for test purposes subaddress f3 (read only) d7 gradelaa [fp-rgb] refer to f4h d6-d0 gradslaa [fp-rgb] lbd: gradient start line of active area internal value, only for test purposes subaddress f4 (read only) d7-d0 gradelaa [fp-rgb] lbd: gradient end line of active area internal value, only for test purposes table 3?8: i 2 c bus command description, continued bit name description
vsp 94x2a data sheet 104 aug. 16, 2004; 6251-552-1ds micronas subaddress f5 (read only) d3 lpblack [fp-rgb] lbd: lower area contains medium brightness level internal value, only for test purposes d2 upblack [fp-rgb] lbd: upper area contains medium brightness level internal value, only for test purposes d1 lpwhite [fp-rgb] lbd: lower area contains high brightness level internal value, only for test purposes d0 upwhite [fp-rgb] lbd: upper area contains high brightness level internal value, only for test purposes subaddress f6h (read-only, compatible to 940x family) d7-d5 version [cp-i2c] version of vsp 94xxx family: ?001?: vsp 94x5b ?010?: vsp 94x2a ?011?: vsp 94x7b ?101?: vsp 94x9c others: reserved d4 sls [cp-i2c] line standard at device output ?0?: 100 hz (vsp 9402a, vsp 9412a) ?1?: 50 hz (vsp 9432a, vsp 9442a) d3-d1 rev [cp-i2c] revision of vsp94x2a ?000?: a23 or below ?001?: a31 or a32 ?010?: b13 or b14 subaddress feh fe any value to this subaddress executes previous i 2 c protocolls immediately subaddress ffh ff any value to this subaddress executes previous i 2 c protocolls according to the take-over-mechanism (dedicated v-pulse, v20, v40, v36) table 3?8: i 2 c bus command description, continued bit name description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 105 4. specifications 4.1. outline dimensions fig. 4?1: pmqfp80-1: p lastic m etric q uad f lat p ackage, 80 leads, 14
vsp 94x2a data sheet 106 aug. 16, 2004; 6251-552-1ds micronas 4.2. pin connections and short descriptions for vsp 9402 and vsp 9412 1) 1) for vsp 9412, the pin connections differ for pins: 1, 2, 3, 75, 76, 77, 78, 79 ,80 (see section 4.3. on page 109). pin no. pin name type connection (if not used) short description 1 vdddacy s/i dac (y) 2 ayout o/i y output 3 vssdacy s/i dac (y) 4 vssd2 s supply voltage for digital (0 v digital) 5 vddd2 s supply voltage for digital (1.8 v digital) 6sda i/o i 2 c-bus data 7 tms i testmode select (connected to vdd33) 8 656vin/blank 1) i/o connect to vss and dis- able blank separate v input for 656 / blank output 9 656clk i/o leave open digital input / output clock 10 656io7 i/o leave open digital input / output (msb) 11 vssp2 s supply voltage for digital (0 v pad) 12 vddp2 s supply voltage for digital (3.3 v pad) 13 scl i i 2 c-bus clk 14 v 2) i connect to vss vertical pulse for rgb input 15 656io6 i/o leave open digital input / output 16 656io5 i/o leave open digital input / output 17 hout o leave open horizontal output (single or double scan, depen- dent on version) 18 h50 3) o leave open hout 50 hz (with skew) 19 adr / tdi i i 2 c address / test data in 20 v50 4) o leave open vout 50 hz 21 656io4 i/o leave open digital input / output 22 656io3 i/o leave open digital input / output 23 vout o leave open vertical output (single or double scan, dependent on version) 24 reset i reset input (reset when low) 25 vddp3 s supply voltage for digital (0 v pad) 26 vssp3 s supply voltage for digital (3.3 v pad)
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 107 27 clkout o leave open output clock (27 mhz nom.) 28 vddd3 s supply voltage for dram (1.8 v digital) 29 vssd3 s supply voltage for digital (0 v digital) 30 656io2 i/o leave open digital input / output 31 656io1 i/o leave open digital input / output 32 656io0 i/o leave open digital input / output (lsb) 33 vssd4 s supply voltage for digital (0 v digital) 34 vddd4 s supply voltage for digital 1.8 v digital 35 vddafbl s supply voltage for fbl (1.8 v) 36 vssafbl s supply voltage for fbl (0 v) 37 fbl1 i connect to vss fast blank input 1 (h1) (analog input) 38 fbl2 i connect to vss fast blank input 2 (h2) (analog input) 39 rin1 i connect to vss r or v in1 (analog input) 40 gin1 i connect to vss g or y in1 (analog input) 41 bin1 i connect to vss b of u in1 (analog input) 42 vddargb s supply voltage for rgb (1.8 v) 43 vssargb s supply voltage for rgb (0 v) 44 vdd33rgb s supply voltage rgb (3.3 v) 45 vss33rgb s supply voltage rgb (0 v) 46 rin2 i connect to vss r or v in2 (analog input) 47 gin2 i connect to vss g or y in2 (analog input) 48 bin2 i connect to vss b of u in2 (analog inpu) 49 vssd5 5) s connect to vss supply voltage for digital (0 v) 50 vddac1 s supply voltage cvbs1 (1.8 v) 51 vssac1 s supply voltage cvbs1 (0 v) 52 cvbs1 i connect to vss cvbs input (analog input) pin no. pin name type connection (if not used) short description
vsp 94x2a data sheet 108 aug. 16, 2004; 6251-552-1ds micronas 53 cvbs2 i connect to vss cvbs input (analog input) 54 cvbs3 i connect to vss cvbs input (analog input) 55 cvbs4 i connect to vss cvbs input or y1 (analog input) 56 cvbs5 i connect to vss cvbs input or c1 (analog input) 57 cvbs6 i connect to vss cvbs input or y2 (analog input) 58 cvbs7 i connect to vss cvbs input or c2 (analog input) 59 vdd33c s supply voltage cvbs (3.3 v) 60 vss33c s supply voltage cvbs (0 v) 61 cvbso3 o leave open cvbs out put 3 (analog output) 62 cvbso2 o leave open cvbs out put 2 (analog output) 63 cvbso1 o leave open cvbs out put 1 (analog output) 64 vddac2 s supply voltage cvbs2 (1.8 v) 65 vssac2 s supply voltage cvbs2 (0 v) 66 vddd1 s supply voltage for digital (1.8 v digital) 67 vssd1 s supply voltage for digital (0 v digital) 68 vddapll s supply voltage for pll (1.8 v) 69 xout o crystal connection 2 70 xin i crystal connection 1 71 tclk i testclock 72 vddp1 s supply voltage for digital (3.3 v pad) 73 vssp1 s supply voltage for digital (0 v pad) 74 656hin/clkf20 i/o connect to vss and dis- able clock separate h input for 656 / 20.25 clock output 75 vdddacv s/i leave open dac (v) (27 mhz nom.) 76 avout o/i leave open v output 77 vssdacv s/i leave open dac (v) 78 vdddacu s/i dac (u) 79 auout o/i u output pin no. pin name type connection (if not used) short description
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 109 4.3. differing pin connections and short descriptions for vsp 9412 80 vssdacu s/i dac (u) 1) in vsp 9402, a31 (and higher) and in vsp 94xxa/b/c, this pin is shared by 656vin and blank. 2) in vsp 94xxb and vsp 94xxc, this pin is shared by v and intr (c800 controller output). 3) in vsp 94xxb and vsp 94xxc, this pin is shared by h50 and irq (data-slicer-interrupt). 4) in vsp 94xxb and vsp 94xxc, this pin is shared by v50 and blank. 5) this pin is not used and not bonded in vsp 9402a. the use of this pin in vsp 94xxb/c will be v ss . for upgradability, it is recommen ded to not leave this pin open. pin no. pin name type connection (if not used) short description 1 i656i5 s/i leave open 656 input 2 i656i6 o/i 656 input 3 i656i7 s/i 656 input (msb) 75 i656iclk s/i 656 input clock 76 i656i0 o/i 656 input (lbs) 77 i656i1 s/i 656 input 78 i656i2 s/i 656 input 79 i656i3 o/i 656 input 80 i656i4 s/i 656 input pin no. pin name type connection (if not used) short description
vsp 94x2a data sheet 110 aug. 16, 2004; 6251-552-1ds micronas 4.4. pin configurations fig. 4?2: pmqfp80-1 package (version vsp 9402a) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1234567891011121314151617181920 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 61 62 63 64 vssac2 vddd1 vssd1 vddapll xout xin tclk vddp1 vssp1 656hin/clkf20 vdddacv avout vssdacv vdddacu auout vssdacu cvbso3 cvbso2 cvbso1 vddac2 vssafbl vddafbl vddd4 vssd4 656io0 656io1 656io2 vssd3 vddd3 clkout vssp3 vddp3 reset vout 656io3 656io4 gin1 rin1 fbl2 fbl1 vdd33c cvbs7 cvbs6 cvbs5 cvbs4 cvbs3 cvbs2 cvbs1 vssac1 vss33c vddac1 vssd5 bin2 gin2 rin2 vss33rgb vdd33rgb vssargb vddargb bin1 ayout vssdacy vssd2 vddd2 sda tms 656vin/blank 656clk 656io7 vddacy vssp2 vddp2 scl v 656io6 656io5 hout h50 adr/tdi v50 vsp 9402 a
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 111 fig. 4?3: pmqfp80-1 package (version vsp 9412a) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1234567891011121314151617181920 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 61 62 63 64 vssac2 vddd1 vssd1 vddapll xout xin tclk vddp1 vssp1 656hin/clkf20 i656iclk i656i0 i656i1 i656i2 i656i3 i656i4 cvbso3 cvbso2 cvbso1 vddac2 vssafbl vddafbl vddd4 vssd4 656io0 656io1 656io2 vssd3 vddd3 clkout vssp3 vddp3 reset vout 656io3 656io4 gin1 rin1 fbl2 fbl1 vdd33c cvbs7 cvbs6 cvbs5 cvbs4 cvbs3 cvbs2 cvbs1 vssac1 vss33c vddac1 vssd5 bin2 gin2 rin2 vss33rgb vdd33rgb vssargb vddargb bin1 i656i6 i656i7 vssd2 vddd2 sda tms 656vin/blank 656clk 656io7 i656i5 vssp2 vddp2 scl v 656io6 656io5 hout h50 adr/tdi v50 vsp 9412 a
vsp 94x2a data sheet 112 aug. 16, 2004; 6251-552-1ds micronas 4.5. pin circuits fig. 4?4: supply pins (ground): vssdacy, vssdacu, vssdacv, vss33c, vss33rgb, vssp1, vssp2, vssp3 fig. 4?5: supply pins (power 3.3 v): vdddacy, vdddacu, vddacv, vdd33c, vdd33rgb, vddp1, vddp2, vddp3 fig. 4?6: input/output pins (crystal connection): xin, xout fig. 4?7: supply pins (power 1.8 v and ground): vddac1, vssac1, vddac2, vssac2, vddargb,vssargb, vddafbl, vssafbl, vddapll, vddd1, vsss1, vddd2, vsss2, vddd3, vsss3, vddd4, vsss4 fig. 4?8: digital output pins: h50, v50, clkout, hout, vout fig. 4?9: digital input pins: v, tms, adr/tdi, reset fig. 4?10: i 2 c bus pins: sda, scl fig. 4?11: digital input/output pins: 656iox,656clk, 656hin/clkf20, 656vin/blank vssp vssb pin vddp vssb pin xout xin oscclk ref (int.) vdd vssb vss pin pin vddp out pin vddp pin in vddp out in pin out vddp pin 500 in
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 113 fig. 4?12: analog output pins: ayout, auout, avout fig. 4?13: analog input pins: rin1, rin2, gin1, gin2, bin1, bin2, fbl1, fbl2, cvbs1...cvbs7 (if cvbsx is connected to any adc) fig. 4?14: analog input pins: cvbs1...cvbs7 (if cvbsx is not connected to any adc) fig. 4?15: analog output pins: cvbso1...cvbso3 vdddac x pin 150 display dac 500 500 in pin vdd 500 300k pin vdd 1v pin vdd out
vsp 94x2a data sheet 114 aug. 16, 2004; 6251-552-1ds micronas 4.6. electrical characteristics abbreviations tbd = to be defined vacant= not applicable positive current values means current flowing into the chip 4.6.1. absolute maximum ratings stresses beyond those listed in the ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only. functional operations of the device at these conditions in not implied exposure to absolute maximum rating conditions for extended periods will affect device reliability. this device contains circuitry to protect the inputs and ou tputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso- lute maximum-rated voltages to this high-impedance circuit. all voltages listed are referenced to ground except where noted. all gnd pins must be connected to a low-resistive ground plane close to the ic. table 4?1: absolute maximum ratings symbol parameter pin name limit values unit min max t a 1) ambient temperature pmqfp80-1 ? ? ? ? ?
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 115 ? table 4?1: absolute maximum ratings symbol parameter pin name limit values unit min max
vsp 94x2a data sheet 116 aug. 16, 2004; 6251-552-1ds micronas i o_high output source current (at 2.4 v) digital outputs 31.7 97.1 ma 1) measured on micronas typical 2-layer (1s1p) board based on jesd - 51.2 standard with maximum power consumption allowed for this package 2) a power-optimized board layout is recommended. the case temperature mentioned in the ?absolute maximum ratings? must not be exceeded at worst case conditions of the application. 3) package limit 4) ? table 4?1: absolute maximum ratings symbol parameter pin name limit values unit min max
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 117 4.6.2. recommended op erating conditions functional operation of the device beyond those indicated in the ?recommended operating conditions/characteris- tics? is not implied and may result in unpredictable behaivior, reduce re liability and lifetime of the device. all voltage listed are referenced to ground except where noted. do not insert the device into a live socket. instead, apply power by switching on the external power supply. symbol parameter pin name limit values unit min typ max t a ambient operating temperature pmqfp80-1 0 ?
vsp 94x2a data sheet 118 aug. 16, 2004; 6251-552-1ds micronas v i,cvbs analog cvbs input voltage cvbs1, cvbs2, cvbs3, cvbs4, cvbs5, cvbs6, cvbs7, rin1, rin2, gin1, gin2, bin1, bin2, fbl1, fbl2 0.6 1.2 1.8 v v i,rgb analog rgb input voltage 0.5 1.2 1.5 v v i,fbl analog fbl input voltage 0.5 1.2 1.5 v analog chroma input voltage (burst) 0.3 v input coupling capacitors cvbs 100 nf input coupling capacitors rgb/fbl 47 nf source resistance 0.1 k ? crystal specification f xtal frequency (fundamental) 3) xin, xout 20.248 20.25 20.252 mhz ? f max /f xtal maximum permissible frequency deviation 3) ? ? f/f xtal recommended permissible frequency deviation 4) ? symbol parameter pin name limit values unit min typ max
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 119 4.6.3. characteristics for min./max. values: at t a = 0 to 70c, f clock =20.25mhz, v sup3.3v = 3.14 to 3.47 v, v sup1.8v = 1.71 to 1.89v for typical values: at t a = 25c, f clock = 20.25mhz, v sup3.3v = 3.14 to 3.47 v, v sup1.8v = 1.71 to 1.89v 4.6.3.1. general characteristics symbol parameter pin name limit values unit test conditions min. typ. max. i ddtot 1.8 v average total supply current 220 ma i ddtot 3.3 v average total supply current 65 ma i ddpd 1.8 v average supply current in power-down-mode 74 ma standby= ?10? i ddpd 3.3 v average supply current in power-down-mode 36 ma standby= ?10? p tot total power dissipation 0.61 0.8 w p totpd total power dissipation in power-down-mode 0.27 w standby= ?10? digital inputs c i input capacitance tms, adr/tdi, v, tclk, reset, 656vin/ blank, 656hin/, 656iox, 656clk, i656ix, i656iclk 7pf input leakage current ? digital outputs v oh output voltage high h50, v50, clkout, hout, vout 2.5 v dd2 v v ol output voltage low 0.6 v i oh output current high ma i ol output current low ma clock outputs t clkout cycle time clkout 37 ns clkout duty cycle 40 60 % t 656clk cycle time 656clk 37 ns 656clk duty cycle 40 60 %
vsp 94x2a data sheet 120 aug. 16, 2004; 6251-552-1ds micronas analog cvbs front-end input leakage current cvbs1, cvbs2, cvbs3, cvbs4, cvbs5, cvbs6, cvbs7 ? ? i clp | input clamping current a dependent on clamping error dnl differential nonlinearity -0.5 0.5 lsb nominal conditions inl integral nonlinearity -1 1 lsb nominal conditions ct crosstalk between cvbs inputs -50 db f sig <5 mhz bw bandwidth 7 mhz -3 db v in input voltage 0.6 1.2 1.8 v a cvbso cvbs output amplification cvbso1, cvbso2, cvbso3 0.9 1.1 analog rgbf front-end input leakage current rin1, rin2, bin1, bin2, gin1, gin2, fbl1, fbl2 ? ? i clp | input clamping current a dependent on clamping error dnl differential nonlinearity ? ? ? digital to analog converters dnl differential nonlinearity auout, auout, avout ? ? ? symbol parameter pin name limit values unit test conditions min. typ. max.
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 121 the listed characteristics are ensured over the operating ran ge of the integrated circuit. typical characteristics spec- ify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a =25 4.6.3.2. i 2 c bus characteristics color decoder/synchronizatio n and luminance processing ? f hf horizontal pll pull-in-range ? ? ? f sc chroma pll pull-in-range symbol parameter pin name limit values unit test conditions min. typ. max. symbol parameter pin name min. typ. max. unit test conditions fast i 2 c bus (all values are referred to min(v ih ) and max(v il )) c b capacitive load/bus line sda/scl 400 pf t r , t f sda/scl rise/fall times 20+$ 300 ns $=0.1 c b /pf t buf inactive time before start of transmission 1300 ns f scl i 2 c clock frequency scl 0 400 khz t low scl low time 1300 ns t high scl high time 600 ns t su;sta set-up time start condition sda 600 ns t hd;sta hold time start condition 600 ns t su;dat set-up time data 100 ns t hd;dat hold time data 0 900 ns t su;sto set-up time stop condition 600 ns i 2 c bus pins v ihr threshold rise sda, scl 2.08 v v il threshold fall 1.8 v
vsp 94x2a data sheet 122 aug. 16, 2004; 6251-552-1ds micronas fig. 4?16: i 2 c bus timing data fig. 4?17: signal flow 940x fig. 4?18: signal flow 941x, 944x, 942x sda in sda out t sp t aa t aa su;sta t hd;sta t f t high t low t hd;dat t su;dat t r t su;sto t buf vsp 940xa vsp 940xb vsp 943xb analog output single-scan 656 input (port 1) vsp 940xa vsp 940xb vsp 943xb analog output single-scan 656 output (943x) or double-scan 656 output (940x) i2c selectable vsp 941xa vsp 941xb vsp 944xb single-scan 656 output (944x) or double-scan 656 output (941x) single-scan 656 input (port 2)
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 123 5. application circuit fig. 5?1: vsp 9402a cvbs1 sda scl y100 v100 u100 q1 20m25 c5 22pf* c6 22pf* l1 10 h +1v8 c24 47nf c25 47nf c23 47nf c15 100 nf ic1 c39 10 f c40 100nf c41 100nf c42 100nf c43 100nf c44 100nf c45 100nf c46 100nf c47 100nf c30 100nf c31 100nf c32 100nf c33 100nf c34 100nf c35 100nf c37 100nf c36 100nf l3 10 h +3.3 v c49 10 f c18 100 nf c19 100 nf c28 47nf c29 47nf c27 47nf r8 3k3 r9 3k3 +3v3 sn7002 sn7002 -- / 47 nf c16 100 nf c17 100 nf c20 100 nf c21 100 nf l2 10 h +1v8 c38 10 f l4 10 h +3.3 v c48 10 f 53 55 54 52 50 64 35 36 7 46 38 39 rin1 37 14 58 57 fbl1 40 gin1 41 bin1 70 xin 69 xout 24 scl 13 sda 56 65 51 71 19 47 48 75 vdddacv 32 656io0 76 avout 2 ayout 79 auout 61 cvbso3 77 vss33rgb 3 vdd33rgb 45 59 78 vssdacv 80 44 1 63 cbbso1 18 h50 62 cvbso2 20 v50 6 vdd33c reset 33 29 4 67 42 43 68 5 66 34 28 12 vddp2 11 vssp2 10 656io7 73 vssp1 72 vddp1 25 vddp3 26 vssp3 vss33c 60 cvbs1 cvbs2 cvbs3 cvbs4 cvbs5 cvbs6 cvbs7 v rin2 fbl2 gin2 bin2 tms tclk adr/tdi vddafbl vssafbl vddac1 vssac1 vddac2 vssac2 vddapll vddargb vssargb vddd1 vssd1 vddd2 vssd2 vddd3 vssd3 vddd4 vssd4 23 vout 27 clkout 17 hout 31 656io1 30 656io2 22 656io3 21 656io4 16 656io5 15 656io6 vdddacu vssdacu vdddacy vssdacy vsp 9402a stepping b13 8 74 9 656clk 656vin/blank 656hin/clkf20 (reserved) 49 cvbso3 cvbso2 cvbso1 mqfp80 t2 t1 +5v t3 t4 t5 3*bc807 r19 51 r20 51 r21 51 c54 33 f c53 33 f c52 33 f cvbs2 cvbs3 cvbs4 cvbs5 cvbs6 cvbs7 hin1/fbl1 bin1 gin1 rin1 fbl2 bin2 gin2 rin2 reset h50 v50 hout vout clkout 656oclk 656out7 656out6 656out5 656out4 656out3 656out2 656out1 656out0 vin1 only for 5v i2c master r1...r7: 7x 75 buffer not necessary when short connection to backend-processor *values are pcb and crystal dependent c22 r21...r27: 8x 75 j1 656vin 656hin 20.25mhz i2c address b2h b0h +3.3v j2 656in7 656in6 656in5 656in4 656in3 656in2 656in1 656in0 656iclk j3 blank
vsp 94x2a data sheet 124 aug. 16, 2004; 6251-552-1ds micronas fig. 5?2: vsp 9412a cvbs1 sda scl l1 10 h +1v8 c24 47nf c25 47nf c23 47nf c15 100 nf ic1 c39 10 f c40 100nf c41 100nf c42 100nf c43 100nf c44 100nf c45 100nf c46 100nf c47 100nf c30 100nf c31 100nf c32 100nf c33 100nf c34 100nf c35 100nf c37 100nf c36 100nf l3 10 h +3.3 v c49 10 f c18 100 nf c19 100 nf c28 47nf c29 47nf c27 47nf r8 3k3 r9 3k3 +3v3 sn7002 sn7002 -- / 47 nf c16 100 nf c17 100 nf c20 100 nf c21 100 nf l2 10 h +1v8 c38 10 f l4 10 h +3.3 v c48 10 f 53 55 54 52 50 64 35 36 7 46 38 39 rin1 37 14 58 57 fbl1 40 gin1 41 bin1 xin xout 24 scl 13 sda 56 65 51 71 19 47 48 75 vdddacv 32 656io0 1 i656i6 75 i656iclk 2 i656i7 80 i656i5 77 vss33rgb 3 vdd33rgb 45 59 78 vssdacv 80 44 1 78 i656i3 77 i656i2 79 i656i4 76 i656i1 6 vdd33c reset 33 29 4 67 42 43 68 5 66 34 28 12 vddp2 11 vssp2 10 656io7 73 vssp1 72 vddp1 25 vddp3 26 vssp3 vss33c 60 cvbs1 cvbs2 cvbs3 cvbs4 cvbs5 cvbs6 cvbs7 v rin2 fbl2 gin2 bin2 tms tclk adr/tdi vddafbl vssafbl vddac1 vssac1 vddac2 vssac2 vddapll vddargb vssargb vddd1 vssd1 vddd2 vssd2 vddd3 vssd3 vddd4 vssd4 23 vout 27 clkout 17 hout 31 656io1 30 656io2 22 656io3 21 656io4 16 656io5 15 656io6 vdddacu vssdacu vdddacy vssdacy vsp 9412a stepping b14 8 74 9 656clk 656vin/blank 656hin/clkf20 (reserved) 49 mqfp80 t2 t1 cvbs2 cvbs3 cvbs4 cvbs5 cvbs6 cvbs7 hin1/fbl1 bin1 gin1 rin1 fbl2 bin2 gin2 rin2 reset hout vout clkout 656oclk 656out7 656out6 656out5 656out4 656out3 656out2 656out1 656out0 vin1 only for 5v i2c master r1...r7: 7x 75 c22 r21...r27: 8x 75 j1 656vin 656hin 20.25mhz i2c address b2h b0h +3.3v j2 j3 blank 656in7 656in6 656in5 656in4 656in3 656in2 656in1 656in0 656iclk i656i0 3 q1 20m25 c5 22pf* c6 22pf* 70 69 *values are pcb and crystal dependent
data sheet vsp 94x2a micronas aug. 16, 2004; 6251-552-1ds 125 5.1. application overview fig. 5?3: application overview with sda 9380 fig. 5?4: application overview with ddp 3315c/ddp 3316c sda 9402 primus sda 9380 eddc sda 6000 m2 sda 5550 tvtpro yuv m u x rgb hd, vd, ew clk rgb, fbl, cor tuner if cvbs cvbs dvd yuv vcr cvbs yc camcorder cvbs, yc rgb rgb h, v h, v vsp 9412a primus ddp 3315c/ ddp 3316c sda 6000 m2 sda 5550 tvtpro ds656 rgb hd, vd, ew clk rgb, fbl, cor tuner if cvbs cvbs dvd yuv vcr cvbs yc camcorder cvbs, yc rgb rgb h, v h, v digital656 mpeg
all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. vsp 94x2a data sheet 126 aug. 16, 2004; 6251-552-1ds micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-552-1ds 6. data sheet history 1. preliminary data sheet: ?vsp 94x2a-b13/b14 powerful scan-rate converter including multistan- dard color decoder?, july 26, 2002, 6251-552-4pd. fourth release of the preliminary data sheet. mayor changes: ?new i 2 c registers added 2. data sheet: ?vsp 94x2a-b13/b14 powerful scan-rate converter including multistan- dard color decoder?, aug. 16, 2004, 6251-552-1ds. first release of the data sheet. major changes: ? version vsp 9432a and vsp 9442a omitted ? section 4. specification updated ? application diagrams updated ? subadress 7bh updated

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